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1. 发明授权

US07961050B1 Integrated circuits including an equalizer and operating methods thereof 有权
标题翻译：集成电路，包括均衡器及其操作方法
公开(公告)号：US07961050B1
公开(公告)日：2011-06-14
申请号：US12706872
申请日：2010-02-17
申请人： Yuwen Swei , Tien-Chun Yang , Chih-Chang Lin , Chan-Hong Chern , Ming-Chieh Huang
发明人： Yuwen Swei , Tien-Chun Yang , Chih-Chang Lin , Chan-Hong Chern , Ming-Chieh Huang
IPC分类号： H03F3/04
CPC分类号： H03F3/45197 , H03F3/45183 , H03F3/45192 , H03F2203/45292 , H03F2203/45458 , H03F2203/45496 , H03F2203/45562 , H03F2203/45631 , H03F2203/45644 , H03F2203/45686 , H03F2203/45702
摘要： An integrated circuit includes a differential amplifier. The differential amplifier includes at least one output end. A circuit is coupled with the at least one output end of the differential amplifier. The circuit does not include a resistor-capacitor (RC) network and is configured for providing a negative impedance to the differential amplifier for adjusting a direct current (DC) gain of the integrated circuit.
摘要翻译：集成电路包括差分放大器。差分放大器包括至少一个输出端。电路与差分放大器的至少一个输出端耦合。该电路不包括电阻 - 电容（RC）网络，并被配置为向差分放大器提供负阻抗以调整集成电路的直流（DC）增益。

2. 发明授权

US09489989B2 Voltage regulators, memory circuits, and operating methods thereof 有权
标题翻译：电压调节器，存储器电路及其操作方法
公开(公告)号：US09489989B2
公开(公告)日：2016-11-08
申请号：US12820712
申请日：2010-06-22
申请人： Ming-Chieh Huang , Chan-Hong Chern , Tien Chun Yang , Chih-Chang Lin , Yuwen Swei
发明人： Ming-Chieh Huang , Chan-Hong Chern , Tien Chun Yang , Chih-Chang Lin , Yuwen Swei
IPC分类号： G11C11/22 , G11C11/24 , G11C7/06 , G11C5/14 , G11C8/00
CPC分类号： G11C11/4074 , G11C5/147
摘要： A voltage regulator includes an output stage electrically coupled with an output end of the voltage regulator. The output stage includes at least one transistor having a bulk and a drain. At least one back-bias circuit is electrically coupled with the bulk of the at least one transistor. The at least one back-bias circuit is configured to provide a bulk voltage, such that the bulk and the drain of the at least one transistor are reverse biased during a standby mode of a memory array that is electrically coupled with the voltage regulator.
摘要翻译：电压调节器包括与电压调节器的输出端电耦合的输出级。输出级包括具有体积和漏极的至少一个晶体管。至少一个背偏置电路与所述至少一个晶体管的主体电耦合。至少一个背偏置电路被配置为提供体电压，使得在与电压调节器电耦合的存储器阵列的待机模式期间，至少一个晶体管的体积和漏极被反向偏置。

3. 发明授权

US08324960B2 Charge pump doubler 有权
标题翻译：电荷泵倍增器
公开(公告)号：US08324960B2
公开(公告)日：2012-12-04
申请号：US12849503
申请日：2010-08-03
申请人： Ming-Chieh Huang , Chan-Hong Chern , Chih-Chang Lin , Tien-Chun Yang , Yuwen Swei
发明人： Ming-Chieh Huang , Chan-Hong Chern , Chih-Chang Lin , Tien-Chun Yang , Yuwen Swei
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H02M3/07
摘要： An integrated circuit includes a first PMOS transistor, where its drain is arranged to be coupled to a voltage output, and its source is coupled to the drain of a second PMOS transistor. The source of the second PMOS transistor is arranged to be coupled to a high power supply voltage. The source and drain of a MOS capacitor are coupled to the source of the first PMOS transistor. The drain of an NMOS transistor is coupled to the drain of the first PMOS transistor. The integrated circuit is configured to receive a voltage input to generate the voltage output having a maximum voltage higher than the voltage input. The gate oxide layer thickness of the MOS capacitor is less than that of the first PMOS transistor.
摘要翻译：集成电路包括第一PMOS晶体管，其中其漏极被布置成耦合到电压输出，并且其源极耦合到第二PMOS晶体管的漏极。第二PMOS晶体管的源极被布置成耦合到高电源电压。 MOS电容器的源极和漏极耦合到第一PMOS晶体管的源极。 NMOS晶体管的漏极耦合到第一PMOS晶体管的漏极。集成电路被配置为接收电压输入以产生具有高于电压输入的最大电压的电压输出。 MOS电容器的栅氧化层厚度小于第一PMOS晶体管的栅极氧化层厚度。

4. 发明授权

US09134360B2 Method and apparatus for feedback-based resistance calibration 有权
标题翻译：用于基于反馈的电阻校准的方法和装置
公开(公告)号：US09134360B2
公开(公告)日：2015-09-15
申请号：US13547101
申请日：2012-07-12
申请人： Tao Wen Chung , Chan-Hong Chern , Ming-Chieh Huang , Chih-Chang Lin , Yuwen Swei
发明人： Tao Wen Chung , Chan-Hong Chern , Ming-Chieh Huang , Chih-Chang Lin , Yuwen Swei
IPC分类号： H03L5/00 , G01R31/26
CPC分类号： G01R31/2621
摘要： A circuit has a first circuit module including a first resistor and first and second transistors coupled in parallel with the first resistor. The first resistor and the first and second transistors are coupled together at a first node. An equivalent resistance across the first circuit module increases as a voltage of the first node is increased from a first voltage to a second voltage, and the equivalent resistance across the first circuit module decreases as the voltage of the first node is increased from the second voltage to a third voltage.
摘要翻译：电路具有包括第一电阻器和与第一电阻器并联耦合的第一和第二晶体管的第一电路模块。第一电阻器和第一和第二晶体管在第一节点耦合在一起。当第一节点的电压从第一电压增加到第二电压时，跨第一电路模块的等效电阻增加，并且第一电路模块上的等效电阻随着第一节点的电压从第二电压增加而减小到第三电压。

5. 发明授权

US08896352B2 Drivers having T-coil structures 有权
标题翻译：驱动器具有T型线圈结构
公开(公告)号：US08896352B2
公开(公告)日：2014-11-25
申请号：US13278742
申请日：2011-10-21
申请人： Ming-Chieh Huang , Tao Wen Chung , Chan-Hong Chern , Chih-Chang Lin , Yuwen Swei , Chiang Pu
发明人： Ming-Chieh Huang , Tao Wen Chung , Chan-Hong Chern , Chih-Chang Lin , Yuwen Swei , Chiang Pu
IPC分类号： H03K3/00
CPC分类号： H03H11/44 , H01S5/0427 , H04B10/504
摘要： A driver includes a first driver stage having at least one input node and at least one first output node. The first driver stage includes a T-coil structure that is disposed adjacent to the at least one first output node. The T-coil structure includes a first set of inductors each being operable to provide a first inductance. A second set of inductors are electrically coupled with the first set of inductors in a parallel fashion. The second set of inductors each are operable to provide a second inductance. A second driver stage is electrically coupled with the first driver stage.
摘要翻译：驱动器包括具有至少一个输入节点和至少一个第一输出节点的第一驱动器级。第一驱动级包括邻近于至少一个第一输出节点设置的T型线圈结构。 T型线圈结构包括第一组电感器，每个电感器可操作以提供第一电感。第二组电感器以并行方式与第一组电感器电耦合。第二组电感器可操作以提供第二电感。第二驱动级与第一驱动器级电耦合。

6. 发明授权

US08766613B2 Method of operating voltage regulator 有权
标题翻译：操作电压调节器的方法
公开(公告)号：US08766613B2
公开(公告)日：2014-07-01
申请号：US13744037
申请日：2013-01-17
申请人： Chan-Hong Chern , Tzu-Ching Chang , Min-Shueh Yuan , Yuwen Swei , Chih-Chang Lin , Chiang Pu , Ming-Chieh Huang , Kuoyuan Hsu
发明人： Chan-Hong Chern , Tzu-Ching Chang , Min-Shueh Yuan , Yuwen Swei , Chih-Chang Lin , Chiang Pu , Ming-Chieh Huang , Kuoyuan Hsu
IPC分类号： G05F1/44
CPC分类号： H02M3/158 , G05F1/44 , G05F1/56
摘要： A method of operating a voltage regulator circuit includes generating a control signal by an amplifier of the voltage regulator circuit. The control signal is generated based on a reference signal at an inverting input of the amplifier and a feedback signal at a non-inverting input of the amplifier. A driving current flowing toward an output node of the voltage regulator circuit is generated by a driver responsive to the control signal, and the driver is coupled between a first power node and the output node. The feedback signal is generated responsive to a voltage level at the output node. A transistor, coupled between the output node and a second power node, is caused to operate in saturation mode during a period while the voltage regulator circuit is operating.
摘要翻译：一种操作电压调节器电路的方法包括由稳压器电路的放大器产生控制信号。控制信号基于放大器的反相输入处的参考信号和放大器的非反相输入端的反馈信号而产生。通过响应于控制信号的驱动器产生朝向电压调节器电路的输出节点流动的驱动电流，并且驱动器耦合在第一功率节点和输出节点之间。响应于输出节点处的电压电平产生反馈信号。耦合在输出节点和第二功率节点之间的晶体管在电压调节器电路工作期间的一段时间内使其工作在饱和模式。

7. 发明授权

US08625240B2 Input/output circuit with inductor 有权
标题翻译：带电感的输入/输出电路
公开(公告)号：US08625240B2
公开(公告)日：2014-01-07
申请号：US13293853
申请日：2011-11-10
申请人： Tao Wen Chung , Chan-Hong Chern , Ming-Chieh Huang , Chih-Chang Lin , Yuwen Swei
发明人： Tao Wen Chung , Chan-Hong Chern , Ming-Chieh Huang , Chih-Chang Lin , Yuwen Swei
IPC分类号： H02H3/22
CPC分类号： H02H9/04 , H01L23/60 , H01L27/0248 , H01L2924/0002 , H03F2200/294 , H03F2203/45638 , H03G1/0023 , H03K3/35613 , H03K19/018514 , H01L2924/00
摘要： An input/output (I/O) circuit includes an electrostatic discharge (ESD) protection circuit electrically coupled with an output node of the I/O circuit. At least one inductor and at least one loading are electrically coupled in a series fashion and between the output node of the I/O circuit and a power line. A circuitry is electrically coupled with a node between the at least one inductor and the at least one loading. The circuitry is operable to increase a current flowing through the at least one inductor during a signal transition.
摘要翻译：输入/输出（I / O）电路包括与I / O电路的输出节点电耦合的静电放电（ESD）保护电路。至少一个电感器和至少一个负载以串联方式电耦合，并且在I / O电路的输出节点和电力线之间。电路与所述至少一个电感器和所述至少一个负载之间的节点电耦合。电路可操作以在信号转换期间增加流过至少一个电感器的电流。

8. 发明授权

US08436671B2 Level shifters having diode-connected devices for input-output interfaces 有权
标题翻译：电平移位器具有用于输入 - 输出接口的二极管连接器件
公开(公告)号：US08436671B2
公开(公告)日：2013-05-07
申请号：US12859456
申请日：2010-08-19
申请人： Chan-Hong Chern , Fu-Lung Hsueh , Chih-Chang Lin , Yuwen Swei , Ming-Chieh Huang
发明人： Chan-Hong Chern , Fu-Lung Hsueh , Chih-Chang Lin , Yuwen Swei , Ming-Chieh Huang
IPC分类号： H03L5/00
CPC分类号： H03K3/02 , H03K19/018521 , H03K19/018528
摘要： A level shifter includes an input node, an output node, a pull-up transistor, a pull-down transistor, and at least one diode-connected device coupled between the pull-up transistor and the pull-down transistor. The level shifter is arranged to be coupled to a high power supply voltage, to receive an input signal having a first voltage level at the input node, and to supply an output signal having a second voltage level at the output node. The high power supply voltage is higher than the first voltage level. The at least one diode-connected device allows the output signal to be pulled up to about a first diode voltage drop below the high power supply voltage and/or to be pulled down to about a second diode voltage drop above ground. The first diode voltage drop and the second diode voltage drop are from the at least one diode-connected device.
摘要翻译：电平移位器包括输入节点，输出节点，上拉晶体管，下拉晶体管以及耦合在上拉晶体管和下拉晶体管之间的至少一个二极管连接器件。电平移位器被布置为耦合到高电源电压，以在输入节点处接收具有第一电压电平的输入信号，并且在输出节点处提供具有第二电压电平的输出信号。高电源电压高于第一电压电平。所述至少一个二极管连接的装置允许输出信号被上拉到大约低于高电源电压的第一二极管电压降和/或被下拉到大约地面上的第二二极管电压降。第一二极管电压降和第二二极管压降来自至少一个二极管连接的器件。

9. 发明申请

US20110285445A1 DRIVE LOOP FOR MEMS OSCILLATOR 有权
标题翻译：用于MEMS振荡器的驱动环
公开(公告)号：US20110285445A1
公开(公告)日：2011-11-24
申请号：US12782064
申请日：2010-05-18
申请人： Ming-Chieh Huang , Chiang Pu , Chan-Hong Chern , Chih-Chang Lin , Yuwen Swei
发明人： Ming-Chieh Huang , Chiang Pu , Chan-Hong Chern , Chih-Chang Lin , Yuwen Swei
IPC分类号： H03L5/00 , H03B5/30 , H02K33/00
CPC分类号： H03B5/30
摘要： Some embodiments regard a method comprising: generating a current according to a movement of the MEMS device; the movement is controlled by a control signal; generating a peak voltage according to the current; and adjusting the control signal when the peak voltage is out of a predetermined range.
摘要翻译：一些实施例涉及一种方法，包括：根据MEMS装置的移动产生电流; 移动由控制信号控制; 根据电流产生峰值电压; 以及当峰值电压超出预定范围时调节控制信号。

10. 发明授权

US08862951B2 Decision feedback equalizer 有权
标题翻译：决策反馈均衡器
公开(公告)号：US08862951B2
公开(公告)日：2014-10-14
申请号：US13528877
申请日：2012-06-21
申请人： Ming-Chieh Huang , Chan-Hong Chern , Tao Wen Chung , Yuwen Swei , Chih-Chang Lin , Tsung-Ching Huang
发明人： Ming-Chieh Huang , Chan-Hong Chern , Tao Wen Chung , Yuwen Swei , Chih-Chang Lin , Tsung-Ching Huang
IPC分类号： G06F11/00 , H04L27/01
CPC分类号： H04L25/03057 , H04L25/06 , H04L25/08
摘要： A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.
摘要翻译：电路包括用于接收输入数据信号和包括先前数据位的反馈信号的求和电路。求和电路被配置为将调节的输入数据信号输出到时钟和数据恢复电路。第一触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第一比特组和具有小于输入数据信号的频率的频率的第一时钟信号由第一求和电路接收。第二触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第二组比特和具有小于输入数据信号的频率的频率的第二时钟信号由第一求和电路接收。

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