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1. 发明授权

US08884665B2 Multiple-phase clock generator 有权
标题翻译：多相时钟发生器
公开(公告)号：US08884665B2
公开(公告)日：2014-11-11
申请号：US13084817
申请日：2011-04-12
申请人： Chih-Chang Lin , Chan-Hong Chern , Ming-Chieh Huang , Tao Wen Chung
发明人： Chih-Chang Lin , Chan-Hong Chern , Ming-Chieh Huang , Tao Wen Chung
IPC分类号： H03B19/00 , H03K5/15
CPC分类号： H03K5/15013
摘要： A multiple-phase clock generator includes at least one stage of dividers. A clock signal is supplied as a first stage clock input to dividers in a first stage of dividers. An N-th stage includes 2N dividers, where N is a positive integer number. Each divider in the first stage is configured to divide a first clock frequency of the first stage clock input by 2 to provide a first stage output. Each divider in the N-th stage is configured to divide an N-th clock frequency of an N-th stage clock input by 2 to provide an N-th stage output. The N-th stage outputs from the dividers in the N-th stage provide 2N-phase clock signals that are equally distributed with a same phase difference between adjacent phase clock signals.
摘要翻译：多相时钟发生器包括至少一个分频器级。时钟信号作为第一级时钟输入提供给分频器的第一级中的分频器。第N级包括2N个分频器，其中N是正整数。第一级中的每个分频器被配置为将第一级时钟输入的第一时钟频率除以2以提供第一级输出。第N级中的每个除法器被配置为将输入的第N级时钟的第N个时钟频率除以2以提供第N级输出。在第N级的分频器的第N级输出提供2N相位时钟信号，它们在相邻的相位时钟信号之间以相同的相位差均匀分布。

2. 发明授权

US08872592B2 High-speed transimpedance amplifier 有权
标题翻译：高速互阻放大器
公开(公告)号：US08872592B2
公开(公告)日：2014-10-28
申请号：US13527365
申请日：2012-06-19
申请人： Tsung-Ching Huang , Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin
发明人： Tsung-Ching Huang , Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin
IPC分类号： H03F3/08
CPC分类号： H03F3/082 , H03F1/0205 , H03F3/08 , H03F3/3022 , H03F3/45179 , H03F3/45183 , H03F2200/216 , H03F2203/30031 , H03F2203/45222 , H03F2203/45644 , H03F2203/45686 , H03F2203/45702 , H03F2203/45724
摘要： A transimpedance amplifier includes a first inverter having a first input node and a first output node. The first input node is configured to be coupled to an input signal. A second inverter has a second input node and a second output node. The second input node is configured to receive a reference voltage terminal. The first inverter and the second inverter are configured to provide a differential output voltage signal between the first output node and the second output node.
摘要翻译：跨阻放大器包括具有第一输入节点和第一输出节点的第一反相器。第一输入节点被配置为耦合到输入信号。第二反相器具有第二输入节点和第二输出节点。第二输入节点被配置为接收参考电压端子。第一反相器和第二反相器被配置为在第一输出节点和第二输出节点之间提供差分输出电压信号。

3. 发明授权

US08862951B2 Decision feedback equalizer 有权
标题翻译：决策反馈均衡器
公开(公告)号：US08862951B2
公开(公告)日：2014-10-14
申请号：US13528877
申请日：2012-06-21
申请人： Ming-Chieh Huang , Chan-Hong Chern , Tao Wen Chung , Yuwen Swei , Chih-Chang Lin , Tsung-Ching Huang
发明人： Ming-Chieh Huang , Chan-Hong Chern , Tao Wen Chung , Yuwen Swei , Chih-Chang Lin , Tsung-Ching Huang
IPC分类号： G06F11/00 , H04L27/01
CPC分类号： H04L25/03057 , H04L25/06 , H04L25/08
摘要： A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.
摘要翻译：电路包括用于接收输入数据信号和包括先前数据位的反馈信号的求和电路。求和电路被配置为将调节的输入数据信号输出到时钟和数据恢复电路。第一触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第一比特组和具有小于输入数据信号的频率的频率的第一时钟信号由第一求和电路接收。第二触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第二组比特和具有小于输入数据信号的频率的频率的第二时钟信号由第一求和电路接收。

4. 发明授权

US08378756B2 Drive loop for MEMS oscillator 有权
标题翻译： MEMS振荡器的驱动环路
公开(公告)号：US08378756B2
公开(公告)日：2013-02-19
申请号：US12782064
申请日：2010-05-18
申请人： Ming-Chieh Huang , Chiang Pu , Chan-Hong Chern , Chih-Chang Lin , Yuwen Swei
发明人： Ming-Chieh Huang , Chiang Pu , Chan-Hong Chern , Chih-Chang Lin , Yuwen Swei
IPC分类号： H03B5/30 , G01C19/00
CPC分类号： H03B5/30
摘要： Some embodiments regard a method comprising: generating a current according to a movement of the MEMS device; the movement is controlled by a control signal; generating a peak voltage according to the current; and adjusting the control signal when the peak voltage is out of a predetermined range.
摘要翻译：一些实施例涉及一种方法，包括：根据MEMS装置的移动产生电流; 移动由控制信号控制; 根据电流产生峰值电压; 以及当峰值电压超出预定范围时调节控制信号。

5. 发明授权

US08354862B2 Phase-lock assistant circuitry 有权
标题翻译：锁相辅助电路
公开(公告)号：US08354862B2
公开(公告)日：2013-01-15
申请号：US13448878
申请日：2012-04-17
申请人： Chih-Chang Lin , Chan-Hong Chern , Steven Swei , Ming-Chieh Huang , Tien-Chun Yang
发明人： Chih-Chang Lin , Chan-Hong Chern , Steven Swei , Ming-Chieh Huang , Tien-Chun Yang
IPC分类号： H03D13/00
CPC分类号： H03L7/08 , H03L7/081 , H03L7/087
摘要： A circuit including a first circuit configured to receive an input signal and first, third and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal. The circuit further includes a second circuit configured to receive an input signal and second, a fourth and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal. The circuit further includes a third circuit configured to generate a first increase signal. The circuit further includes a fourth circuit configured to generate a first decrease signal.
摘要翻译：包括被配置为接收输入信号和时钟的第一，第三和第五相位时钟并且产生指示时钟的第一早期信号的第一电路的电路早于输入信号，并且指示时钟的第一晚信号晚于输入信号。电路还包括配置成接收时钟的输入信号和第二，第四和第六相位时钟的第二电路，并且产生指示时钟早于输入信号的第二早期信号，并且指示时钟的第二延迟信号是晚于输入信号。电路还包括被配置为产生第一增加信号的第三电路。电路还包括被配置为产生第一减小信号的第四电路。

6. 发明授权

US08179162B2 Phase-lock assistant circuitry 有权
标题翻译：锁相辅助电路
公开(公告)号：US08179162B2
公开(公告)日：2012-05-15
申请号：US12835130
申请日：2010-07-13
申请人： Chih-Chang Lin , Chan-Hong Chern , Steven Swei , Ming-Chieh Huang , Tien-Chun Yang
发明人： Chih-Chang Lin , Chan-Hong Chern , Steven Swei , Ming-Chieh Huang , Tien-Chun Yang
IPC分类号： H03D13/00 , H03L7/06
CPC分类号： H03L7/08 , H03L7/081 , H03L7/087
摘要： Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.
摘要翻译：一些实施例涉及一种电路，包括：第一电路，其被配置为将输出时钟的频率锁定到参考时钟的频率; 第二电路，被配置为将输入信号与所述输出时钟的相位时钟对准; 第三电路，被配置为使用所述输出时钟的第一组相位时钟和所述输出时钟的第二组相位时钟，以改善所述输入信号与所述输出时钟的相位时钟的对准; 以及锁定检测电路，被配置为当所述输出时钟的频率未被锁定到所述参考时钟的频率时接通所述第一电路; 并且当输出时钟的频率被锁定到参考时钟的频率时，关闭第一电路并接通第二电路和第三电路。

7. 发明申请

US20110199152A1 INTEGRATED CIRCUITS INCLUDING A CHARGE PUMP CIRCUIT AND OPERATING METHODS THEREOF 有权
标题翻译：集成电路，包括充电泵电路及其工作方法
公开(公告)号：US20110199152A1
公开(公告)日：2011-08-18
申请号：US12706886
申请日：2010-02-17
申请人： Steven SWEI , Chih-Chang Lin , Tien-Chun Yang , Chan-Hong Chern , Ming-Chieh Huang
发明人： Steven SWEI , Chih-Chang Lin , Tien-Chun Yang , Chan-Hong Chern , Ming-Chieh Huang
IPC分类号： G05F1/10
CPC分类号： G05F1/10 , G05F3/02 , H03L7/0895 , H03L7/0896 , H03L7/0898
摘要： An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.
摘要翻译：集成电路包括第一电流源。第二电流源经由导线与第一电流源电耦合。开关电路耦合在第一电流源和第二电流源之间。第一电路耦合在第一节点和第二节点之间。第一节点设置在第一电流源和开关电路之间。第二节点与第一电流源耦合。第一电路被配置为基本上均衡第一节点和第二节点上的电压。第二电路耦合在第三节点和第四节点之间。第三节点设置在第二电流源和开关电路之间。第四节点被布置成与第二电流源耦合。第二电路被配置为基本上均衡第三节点和第四节点上的电压。

8. 发明授权

US09489989B2 Voltage regulators, memory circuits, and operating methods thereof 有权
标题翻译：电压调节器，存储器电路及其操作方法
公开(公告)号：US09489989B2
公开(公告)日：2016-11-08
申请号：US12820712
申请日：2010-06-22
申请人： Ming-Chieh Huang , Chan-Hong Chern , Tien Chun Yang , Chih-Chang Lin , Yuwen Swei
发明人： Ming-Chieh Huang , Chan-Hong Chern , Tien Chun Yang , Chih-Chang Lin , Yuwen Swei
IPC分类号： G11C11/22 , G11C11/24 , G11C7/06 , G11C5/14 , G11C8/00
CPC分类号： G11C11/4074 , G11C5/147
摘要： A voltage regulator includes an output stage electrically coupled with an output end of the voltage regulator. The output stage includes at least one transistor having a bulk and a drain. At least one back-bias circuit is electrically coupled with the bulk of the at least one transistor. The at least one back-bias circuit is configured to provide a bulk voltage, such that the bulk and the drain of the at least one transistor are reverse biased during a standby mode of a memory array that is electrically coupled with the voltage regulator.
摘要翻译：电压调节器包括与电压调节器的输出端电耦合的输出级。输出级包括具有体积和漏极的至少一个晶体管。至少一个背偏置电路与所述至少一个晶体管的主体电耦合。至少一个背偏置电路被配置为提供体电压，使得在与电压调节器电耦合的存储器阵列的待机模式期间，至少一个晶体管的体积和漏极被反向偏置。

9. 发明授权

US08854104B2 Voltage level shifter 有权
标题翻译：电压电平转换器
公开(公告)号：US08854104B2
公开(公告)日：2014-10-07
申请号：US13793681
申请日：2013-03-11
申请人： Tao Wen Chung , Chan-Hong Chern , Tsung-Ching (Jim) Huang , Chih-Chang Lin , Ming-Chieh Huang
发明人： Tao Wen Chung , Chan-Hong Chern , Tsung-Ching (Jim) Huang , Chih-Chang Lin , Ming-Chieh Huang
IPC分类号： H03L5/00
CPC分类号： H03L5/00 , H03K3/356182 , H03K17/102 , H03K19/018521
摘要： A circuit includes a first capacitive device and a first latch. The first capacitive device includes a first end configured to receive a first input signal and a second end coupled with the first latch. The first latch includes a first transistor and a second transistor that are of a first type. A first terminal of the first transistor and a first terminal of the second transistor are each configured to receive a first voltage value. A second terminal of the first transistor is coupled with a third terminal of the second transistor. A third terminal of the first transistor is coupled with a second terminal of the second transistor and with the second end of the capacitive device, and is configured to provide an output voltage for the first latch.
摘要翻译：电路包括第一电容性装置和第一锁存器。第一电容性装置包括被配置为接收第一输入信号的第一端和与第一锁存器耦合的第二端。第一锁存器包括第一类型的第一晶体管和第二晶体管。第一晶体管的第一端子和第二晶体管的第一端子都被配置为接收第一电压值。第一晶体管的第二端与第二晶体管的第三端耦合。第一晶体管的第三端子与第二晶体管的第二端子和电容器件的第二端耦合，并且被配置为提供用于第一锁存器的输出电压。

10. 发明授权

US08766613B2 Method of operating voltage regulator 有权
标题翻译：操作电压调节器的方法
公开(公告)号：US08766613B2
公开(公告)日：2014-07-01
申请号：US13744037
申请日：2013-01-17
申请人： Chan-Hong Chern , Tzu-Ching Chang , Min-Shueh Yuan , Yuwen Swei , Chih-Chang Lin , Chiang Pu , Ming-Chieh Huang , Kuoyuan Hsu
发明人： Chan-Hong Chern , Tzu-Ching Chang , Min-Shueh Yuan , Yuwen Swei , Chih-Chang Lin , Chiang Pu , Ming-Chieh Huang , Kuoyuan Hsu
IPC分类号： G05F1/44
CPC分类号： H02M3/158 , G05F1/44 , G05F1/56
摘要： A method of operating a voltage regulator circuit includes generating a control signal by an amplifier of the voltage regulator circuit. The control signal is generated based on a reference signal at an inverting input of the amplifier and a feedback signal at a non-inverting input of the amplifier. A driving current flowing toward an output node of the voltage regulator circuit is generated by a driver responsive to the control signal, and the driver is coupled between a first power node and the output node. The feedback signal is generated responsive to a voltage level at the output node. A transistor, coupled between the output node and a second power node, is caused to operate in saturation mode during a period while the voltage regulator circuit is operating.
摘要翻译：一种操作电压调节器电路的方法包括由稳压器电路的放大器产生控制信号。控制信号基于放大器的反相输入处的参考信号和放大器的非反相输入端的反馈信号而产生。通过响应于控制信号的驱动器产生朝向电压调节器电路的输出节点流动的驱动电流，并且驱动器耦合在第一功率节点和输出节点之间。响应于输出节点处的电压电平产生反馈信号。耦合在输出节点和第二功率节点之间的晶体管在电压调节器电路工作期间的一段时间内使其工作在饱和模式。

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