专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20190206727A1 SEMICONDUCTOR DEVICES INCLUDING A STAIR STEP STRUCTURE, AND RELATED METHODS 审中-公开
公开(公告)号：US20190206727A1
公开(公告)日：2019-07-04
申请号：US16172218
申请日：2018-10-26
申请人： Micron Technology, Inc.
发明人： John B. Matovu , David S. Meyaard , Gowrisankar Damarla , Sri Sai Sivakumar Vegunta , Kunal Shrotri , Shashank Saraf , Kevin R. Gast , Jivaan Kishore Jhothiraman , Suresh Ramarajan , Lifang Xu , Rithu K. Bhonsle , Rutuparna Narulkar , Matthew J. King
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528 , H01L27/11556 , H01L27/11582
摘要： A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material. Related methods of forming semiconductor structures and related semiconductor devices are disclosed.

2. 发明申请

US20170331032A1 Magnetic Tunnel Junctions 审中-公开
公开(公告)号：US20170331032A1
公开(公告)日：2017-11-16
申请号：US15588994
申请日：2017-05-08
申请人： Micron Technology, Inc.
发明人： Wei Chen , Witold Kula , Manzar Siddik , Suresh Ramarajan , Jonathan D. Harms
IPC分类号： H01L43/02 , H01L43/10 , H01L27/22
CPC分类号： H01L43/02 , G11C11/161 , H01L27/224 , H01L43/08 , H01L43/10
摘要： A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material, a conductive second magnetic electrode spaced from the first electrode and comprising magnetic reference material, and a non-magnetic tunnel insulator material between the first and second electrodes. The magnetic reference material of the second electrode comprises a synthetic antiferromagnetic construction comprising two spaced magnetic regions one of which is closer to the tunnel insulator material than is the other. The one magnetic region comprises a polarizer region comprising CoxFeyBz where “x” is from 0 to 90, “y” is from 10 to 90, and “z” is from 10 to 50. The CoxFeyBz is directly against the tunnel insulator. A non-magnetic region comprising an Os-containing material is between the two spaced magnetic regions. The other magnetic region comprises a magnetic Co-containing material. Other embodiments are disclosed.

3. 发明申请

US20160211440A1 SEMICONDUCTOR DEVICES, MAGNETIC TUNNEL JUNCTIONS, AND METHODS OF FABRICATION THEREOF 审中-公开
标题翻译：半导体器件，磁性隧道结及其制造方法
公开(公告)号：US20160211440A1
公开(公告)日：2016-07-21
申请号：US14597903
申请日：2015-01-15
申请人： Micron Technology, Inc.
发明人： Manzar Siddik , Witold Kula , Suresh Ramarajan
IPC分类号： H01L43/08 , G11C11/16 , H01L43/12 , H01L43/02 , H01L43/10
CPC分类号： H01L43/08 , G11C11/161 , H01L43/12
摘要： A semiconductor device comprises an array of magnetic cell structures each comprising a magnetic tunnel junction over an electrode on a substrate. Each of the magnetic tunnel junctions includes a magnetic material over the substrate, a first tunnel barrier material over the magnetic material, a second tunnel barrier material over the annealed first tunnel barrier material, and another magnetic material over the second tunnel barrier material. Each magnetic tunnel junction is configured to exhibit a tunnel magnetoresistance greater than or equal to about 180% at a resistance area product of less than about 8 ohm μm2. The semiconductor device also includes another electrode over the another magnetic material. Semiconductor devices including the magnetic tunnel junctions, methods of forming the magnetic tunnel junctions, and methods of forming semiconductor devices including the magnetic tunnel junctions are disclosed.
摘要翻译：半导体器件包括磁性单元结构的阵列，每个磁性单元结构包括在衬底上的电极上的磁性隧道结。每个磁性隧道结包括在该基底上的磁性材料，在该磁性材料上方的第一隧道阻挡材料，该退火的第一隧道屏障材料上方的第二隧道阻挡材料，以及该第二隧道屏障材料上的另一种磁性材料。每个磁性隧道结被配置为在小于约8欧姆·μm2的电阻面积产生大于或等于约180％的隧道磁阻。半导体器件还包括在另一磁性材料上的另一电极。公开了包括磁隧道结的半导体器件，形成磁隧道结的方法，以及形成包括磁性隧道结的半导体器件的方法。

4. 发明申请

US20210050252A1 APPARATUS COMPRISING STRUCTURES INCLUDING CONTACT VIAS AND CONDUCTIVE LINES, RELATED METHODS, AND MEMORY DEVICES 有权
公开(公告)号：US20210050252A1
公开(公告)日：2021-02-18
申请号：US16542507
申请日：2019-08-16
申请人： Micron Technology, Inc.
发明人： Xiaosong Zhang , Yongjun J. Hu , David A. Kewley , Md Zahid Hossain , Michael J. Irwin , Daniel Billingsley , Suresh Ramarajan , Robert J. Hanson , Biow Hiem Ong , Keen Wah Chow
IPC分类号： H01L21/768
摘要： An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.

5. 发明授权

US10600682B2 Semiconductor devices including a stair step structure, and related methods 有权
公开(公告)号：US10600682B2
公开(公告)日：2020-03-24
申请号：US16172218
申请日：2018-10-26
申请人： Micron Technology, Inc.
发明人： John B. Matovu , David S. Meyaard , Gowrisankar Damarla , Sri Sai Sivakumar Vegunta , Kunal Shrotri , Shashank Saraf , Kevin R. Gast , Jivaan Kishore Jhothiraman , Suresh Ramarajan , Lifang Xu , Rithu K. Bhonsle , Rutuparna Narulkar , Matthew J. King
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528 , H01L21/3105 , H01L27/11582 , H01L27/11556 , H01L27/11575 , H01L27/11548
摘要： A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material. Related methods of forming semiconductor structures and related semiconductor devices are disclosed.

6. 发明授权

US10269625B1 Methods of forming semiconductor structures having stair step structures 有权
公开(公告)号：US10269625B1
公开(公告)日：2019-04-23
申请号：US15857197
申请日：2017-12-28
申请人： Micron Technology, Inc.
发明人： John B. Matovu , David S. Meyaard , Gowrisankar Damarla , Sri Sai Sivakumar Vegunta , Kunal Shrotri , Shashank Saraf , Kevin R. Gast , Jivaan Kishore Jhothiraman , Suresh Ramarajan , Lifang Xu , Rithu K. Bhonsle , Rutuparna Narulkar , Matthew J. King
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528 , H01L27/11582 , H01L27/11556
摘要： A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material. Related methods of forming semiconductor structures and related semiconductor devices are disclosed.

7. 发明授权

US09593431B2 Electroplating systems 有权
标题翻译：电镀系统
公开(公告)号：US09593431B2
公开(公告)日：2017-03-14
申请号：US13863916
申请日：2013-04-16
申请人： Micron Technology, Inc.
发明人： Suresh Ramarajan , Whonchee Lee
IPC分类号： C25D17/00 , C25D7/12 , C25D17/12 , H01L21/288 , C25D5/18 , C25D17/10
CPC分类号： C25D17/002 , C25D5/18 , C25D7/123 , C25D17/001 , C25D17/10 , C25D17/12 , H01L21/2885
摘要： Electroplating systems that include a plurality of electrodes, a power supply operably coupled to the plurality of electrodes, a platen for bearing a substrate on which metal features are to be formed, and an electrode support are disclosed. The electrode support may be configured for suspending the electrode assembly over an upper surface of the substrate disposed on the platen in spaced relation to and in alignment with the substrate or for supporting the electrode assembly in a stationary position over the substrate when the voltage is applied across the plurality of electrodes. The electrodes may be adjacent, mutually spaced and electrically isolated and connected in series so as to be oppositely polarized when the voltage is applied thereacross or may be connected so as to have alternating polarities when the voltage is applied thereacross.
摘要翻译：公开了包括多个电极的电镀系统，可操作地耦合到多个电极的电源，用于承载要形成金属特征的基板的压板和电极支撑件。电极支撑件可以被配置用于将电极组件悬挂在设置在压板上的衬底的上表面上，该衬底的上表面与衬底间隔开并与之对准，或者当施加电压时，将电极组件支撑在衬底上的静止位置跨越多个电极。电极可以相邻，相互间隔并且电隔离并且串联连接，以便当在其上施加电压时可以相反地极化，或者可以在电压施加到其上时具有交替极性。

8. 发明授权

US11101171B2 Apparatus comprising structures including contact vias and conductive lines, related methods, and memory devices 有权
公开(公告)号：US11101171B2
公开(公告)日：2021-08-24
申请号：US16542507
申请日：2019-08-16
申请人： Micron Technology, Inc.
发明人： Xiaosong Zhang , Yongjun J. Hu , David A. Kewley , Md Zahid Hossain , Michael J. Irwin , Daniel Billingsley , Suresh Ramarajan , Robert J. Hanson , Biow Hiem Ong , Keen Wah Chow
IPC分类号： H01L21/768
摘要： An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.

9. 发明授权

US10439131B2 Methods of forming semiconductor devices including tunnel barrier materials 有权
公开(公告)号：US10439131B2
公开(公告)日：2019-10-08
申请号：US14597903
申请日：2015-01-15
申请人： Micron Technology, Inc.
发明人： Manzar Siddik , Witold Kula , Suresh Ramarajan
IPC分类号： H01L43/12 , H01L43/08 , G11C11/16
摘要： A semiconductor device comprises an array of magnetic cell structures each comprising a magnetic tunnel junction over an electrode on a substrate. Each of the magnetic tunnel junctions includes a magnetic material over the substrate, a first tunnel barrier material over the magnetic material, a second tunnel barrier material over the annealed first tunnel barrier material, and another magnetic material over the second tunnel barrier material. Each magnetic tunnel junction is configured to exhibit a tunnel magnetoresistance greater than or equal to about 180% at a resistance area product of less than about 8 ohm μm2. The semiconductor device also includes another electrode over the another magnetic material. Semiconductor devices including the magnetic tunnel junctions, methods of forming the magnetic tunnel junctions, and methods of forming semiconductor devices including the magnetic tunnel junctions are disclosed.

10. 发明申请

US20190305211A1 Magnetic Tunnel Junctions 审中-公开
公开(公告)号：US20190305211A1
公开(公告)日：2019-10-03
申请号：US16434634
申请日：2019-06-07
申请人： Micron Technology, Inc.
发明人： Wei Chen , Witold Kula , Manzar Siddik , Suresh Ramarajan , Jonathan D. Harms
IPC分类号： H01L43/02 , H01L27/22 , H01L43/10 , H01L43/08 , G11C11/16
摘要： A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material, a conductive second magnetic electrode spaced from the first electrode and comprising magnetic reference material, and a non-magnetic tunnel insulator material between the first and second electrodes. The magnetic reference material of the second electrode comprises a synthetic antiferromagnetic construction comprising two spaced magnetic regions one of which is closer to the tunnel insulator material than is the other. The one magnetic region comprises a polarizer region comprising CoxFeyBz where “x” is from 0 to 90, “y” is from 10 to 90, and “z” is from 10 to 50. The CoxFeyBz is directly against the tunnel insulator. A non-magnetic region comprising an Os-containing material is between the two spaced magnetic regions. The other magnetic region comprises a magnetic Co-containing material. Other embodiments are disclosed.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式