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1. 发明授权

US6159795A Low voltage junction and high voltage junction optimization for flash memory 失效
标题翻译：闪存的低电压结和高压结优化
公开(公告)号：US6159795A
公开(公告)日：2000-12-12
申请号：US109664
申请日：1998-07-02
申请人： Masaaki Higashitani , Hao Fang , Narbeh Derhacobian
发明人： Masaaki Higashitani , Hao Fang , Narbeh Derhacobian
IPC分类号： H01L21/8247 , H01L27/105 , H01L21/336 , H01L21/8234
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546 , Y10S438/976
摘要： An intermediate implant step is performed to optimize the performance of the transistors in the peripheral portion of a floating gate type memory integrated circuit. The polysilicon layer (Poly 1) that forms the floating gate in the respective floating gate type memory devices prevents penetration of the optimizing implant into the core region in which the floating gate memory devices are formed. This permits the optimization implant to be performed without the need for an additional mask, thus reducing costs and production time.
摘要翻译：执行中间植入步骤以优化浮动型存储器集成电路的周边部分中的晶体管的性能。在相应的浮动栅型存储器件中形成浮置栅极的多晶硅层（Poly 1）防止优化注入穿透到形成浮栅存储器件的芯区域中。这允许在不需要附加掩模的情况下执行优化植入，从而降低成本和生产时间。

2. 发明授权

US6143608A Barrier layer decreases nitrogen contamination of peripheral gate regions during tunnel oxide nitridation 有权
标题翻译：阻挡层在隧道氧化物氮化期间减少外围栅极区域的氮污染
公开(公告)号：US6143608A
公开(公告)日：2000-11-07
申请号：US283308
申请日：1999-03-31
申请人： Yue-Song He , Masaaki Higashitani , Hao Fang , Narbeh Derhacobian , Bill Cox , Kent Chang , Kelwin Ko , Maria Chow-Chan
发明人： Yue-Song He , Masaaki Higashitani , Hao Fang , Narbeh Derhacobian , Bill Cox , Kent Chang , Kelwin Ko , Maria Chow-Chan
IPC分类号： H01L21/8247 , H01L27/105 , H01L21/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11536
摘要： This invention describes methods for producing gate oxide regions in periphery regions of semiconductor chips, wherein the gate oxide regions have improved electrical properties. The methods involve the deposition of a barrier layer over the periphery of the semiconductor chip to prevent the introduction of contaminating nitrogen atoms into the periphery during a nitridation step in the core region of the semiconductor chip. By preventing the contamination of the gate areas of the periphery, the gate oxide regions so produced have increased breakdown voltages and increased reliability. This invention describes methods for etching the barrier layers used to protect the periphery from tunnel oxide nitridation. Semiconductor devices made with the methods of this invention have longer expected lifetimes and can be manufactured with higher device density.
摘要翻译：本发明描述了在半导体芯片的周边区域中制造栅极氧化物区域的方法，其中栅极氧化物区域具有改善的电性能。所述方法包括在半导体芯片的周边上沉积阻挡层，以防止在半导体芯片的芯区域中的氮化步骤期间将杂质氮原子引入周围。通过防止周围的栅极区域的污染，如此产生的栅极氧化物区域具有增加的击穿电压和增加的可靠性。本发明描述了用于蚀刻用于保护周边免受隧道氧化物氮化的阻挡层的方法。用本发明的方法制造的半导体器件具有更长的预期寿命，并且可以以较高的器件密度制造。

3. 发明授权

US06369433B1 High voltage transistor with low body effect and low leakage 有权
标题翻译：具有低体积效应和低泄漏的高压晶体管
公开(公告)号：US06369433B1
公开(公告)日：2002-04-09
申请号：US09182525
申请日：1998-10-30
申请人： Narbeh Derhacobian , Pau-ling Chen , Hao Fang
发明人： Narbeh Derhacobian , Pau-ling Chen , Hao Fang
IPC分类号： H01L2994
CPC分类号： H01L29/66575 , H01L21/823807 , H01L21/823814 , H01L29/1041 , H01L29/66825
摘要： A high voltage transistor exhibiting low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a field implant blocking mask over the channel area, thereby producing a transistor with low body effect, the field implant blocking mask having appropriate openings so that the field implant occurs at the edges of the channel, thereby reducing leakage.
摘要翻译：形成具有低泄漏和低体效应的高压晶体管，同时避免过多数量的昂贵的掩蔽步骤。实施例包括在通道区域上提供场注入阻挡掩模，从而产生具有低体效应的晶体管，场注入阻挡掩模具有适当的开口，使得场注入发生在通道的边缘，从而减少泄漏。

4. 发明授权

US06177322B1 High voltage transistor with high gated diode breakdown voltage 有权
标题翻译：具有高门极二极管击穿电压的高压晶体管
公开(公告)号：US06177322B1
公开(公告)日：2001-01-23
申请号：US09177817
申请日：1998-10-23
申请人： Narbeh Derhacobian , Pau-Ling Chen , Hao Fang , Timothy Thurgate
发明人： Narbeh Derhacobian , Pau-Ling Chen , Hao Fang , Timothy Thurgate
IPC分类号： H01L21336
CPC分类号： H01L29/66575 , H01L29/1033 , H01L29/41775
摘要： A high voltage transistor exhibiting high gated diode breakdown voltage is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant, masking the source/drain regions from the conventional threshold adjust implant, providing a thick gate oxide layer, employing a very lightly doped n-type implant in lieu of conventional n+ and LDD implants, and forming contacts to the source and drain regions at a minimum distance from the gate.
摘要翻译：形成表现出高选通二极管击穿电压的高压晶体管，同时避免过多数量的昂贵的掩蔽步骤。实施例包括通过掩盖来自常规场注入的高电压接头来提供高门控二极管击穿电压，从常规阈值调整注入屏蔽源极/漏极区域，提供厚栅极氧化物层，采用非常轻掺杂的n型注入代替常规的n +和LDD植入物，并且在与栅极最小距离处形成与源区和漏区的接触。

5. 发明授权

US6166951A Multi state sensing of NAND memory cells by applying reverse-bias voltage 有权
标题翻译：通过施加反向偏置电压对NAND存储单元进行多状态感测
公开(公告)号：US6166951A
公开(公告)日：2000-12-26
申请号：US370010
申请日：1999-08-06
申请人： Narbeh Derhacobian , Hao Fang , Michael Han
发明人： Narbeh Derhacobian , Hao Fang , Michael Han
IPC分类号： G11C11/56 , G11C16/04 , G11C16/26
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5642 , G11C16/26 , G11C2211/5642
摘要： A method and circuit for sensing multi states of a NAND memory cell by applying reverse bias voltage at a constant gate voltage, preferably zero volts, generating a memory cell current in response to the applied reverse P well bias, and sensing the memory cell state.
摘要翻译：一种用于通过以恒定栅极电压（优选为零伏特）施加反向偏置电压来感测NAND存储器单元的多种状态的方法和电路，响应于所施加的反向P阱偏置而产生存储单元电流，以及感测存储单元状态。

6. 发明授权

US06514830B1 Method of manufacturing high voltage transistor with modified field implant mask 有权
标题翻译：使用改进的场注入掩模制造高压晶体管的方法
公开(公告)号：US06514830B1
公开(公告)日：2003-02-04
申请号：US10044510
申请日：2002-01-11
申请人： Hao Fang , Narbeh Derhacobian
发明人： Hao Fang , Narbeh Derhacobian
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/11534
摘要： A method of manufacturing a high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect while avoiding an excessive number of costly masking steps. A high gated diode breakdown voltage is provided in the manufacturing process by masking the high voltage junctions from the conventional field implant and masking the source/drain regions from the conventional threshold adjust implant. Angled openings are formed in the field implant blocking mask so that the field implant at varying distances away from the junctions, thus achieving low leakage and a high gated diode breakdown voltage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.
摘要翻译：一种制造高栅极二极管击穿电压，低泄漏和低体效应的高压晶体管的方法，同时避免过多数量的昂贵的掩蔽步骤。在制造过程中通过掩蔽来自常规场注入的高压结和从常规阈值调整植入物屏蔽源极/漏极区域来提供高栅极二极管击穿电压。在场注入阻挡掩模中形成有角度的开口，使得场离子注入距离结点不同的距离，从而实现低泄漏和高门控二极管击穿电压。场注入阻挡掩模在沟道区域上延伸，从而产生具有低体效应的晶体管。

7. 发明授权

US06351017B1 High voltage transistor with modified field implant mask 有权
标题翻译：具有改进的场注入掩模的高压晶体管
公开(公告)号：US06351017B1
公开(公告)日：2002-02-26
申请号：US09533057
申请日：2000-03-22
申请人： Hao Fang , Narbeh Derhacobian
发明人： Hao Fang , Narbeh Derhacobian
IPC分类号： H01L31119
CPC分类号： H01L27/11526 , H01L27/11534
摘要： A high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant and masking the source/drain regions from the conventional threshold adjust implant. Angled openings are formed in the field implant blocking mask so that the field implant at varying distances away from the junctions, thus achieving low leakage and a high gated diode breakdown voltage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.
摘要翻译：形成具有高门控二极管击穿电压，低泄漏和低体效应的高电压晶体管，同时避免过多数量的昂贵的掩蔽步骤。实施例包括通过掩蔽来自常规场注入的高电压结以及从常规阈值调整植入物屏蔽源/漏区来提供高门控二极管击穿电压。在场注入阻挡掩模中形成有角度的开口，使得场离子注入距离结点不同的距离，从而实现低泄漏和高门控二极管击穿电压。场注入阻挡掩模在沟道区域上延伸，从而产生具有低体效应的晶体管。

8. 发明授权

US06228782B1 Core field isolation for a NAND flash memory 有权
标题翻译： NAND闪存的核心现场隔离
公开(公告)号：US06228782B1
公开(公告)日：2001-05-08
申请号：US09309994
申请日：1999-05-11
申请人： Hao Fang , Massaki Higashitani , Narbeh Derhacobian
发明人： Hao Fang , Massaki Higashitani , Narbeh Derhacobian
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/76216 , H01L27/115
摘要： Selective high-energy impurity implantation enables optimization of both core and peripheral field isolation without substantially degrading functionality, self-boosting efficiency or otherwise increasing program disturb, thereby improving device performance and reliability. Embodiments include high-energy impurity implantation, after forming core and peripheral field oxide regions in a semiconductor substrate, into the peripheral field oxide region and selected portions of the core field oxide regions corresponding to select transistor areas, while blocking the implant from the core memory cell channel regions. A channel stop implant is performed through the core field oxide regions after etching a first polysilicon layer. The high-energy impurity implant optimizes peripheral field isolation, without degrading self-boosting efficiency, because it is blocked from entering the memory cell channel region. The high-energy implant also enhances isolation in the select transistor areas, thereby preventing an increase in device malfunctions, while the channel stop implant optimizes core field isolation.
摘要翻译：选择性高能杂质注入使得能够优化核和外围场隔离，而不会显着降低功能性，自增强效率或以其他方式增加程序干扰，从而提高器件性能和可靠性。实施例包括在半导体衬底中形成核心和外围场氧化物区域之后的高能杂质注入到对应于选择晶体管区域的外围场氧化物区域和核心场氧化物区域的选定部分，同时将核心存储器细胞通道区。在蚀刻第一多晶硅层之后，通过核心场氧化物区域进行沟道停止注入。高能杂质注入优化外围场隔离，而不会降低自增强效率，因为它被阻止进入存储单元通道区。高能量注入还增强了选择晶体管区域的隔离度，从而防止了器件故障的增加，而通道停止植入则优化了磁芯隔离。

9. 发明授权

US5991202A Method for reducing program disturb during self-boosting in a NAND flash memory 有权
标题翻译：用于在NAND闪速存储器中自增强期间减少编程干扰的方法
公开(公告)号：US5991202A
公开(公告)日：1999-11-23
申请号：US161423
申请日：1998-09-24
申请人： Narbeh Derhacobian , Hao Fang
发明人： Narbeh Derhacobian , Hao Fang
IPC分类号： G11C16/04 , G11C16/10 , G11C11/34
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/10
摘要： A NAND flash memory system is programmed with minimal program disturb and pass disturb during self-boosting without resorting to impurity implantation for bit line isolation, to p-well biasing or to bit line biasing techniques. A program voltage is applied to a selected word line in the form of a plurality of short pulses while synchronously applying a pulsed pass voltage to the unselected word lines until the selected cell is programmed. The duration of the pulses and the time between pulses are chosen to minimize the program disturb of unselected cells, especially unselected cells on the selected word line, without causing pass disturb of any cell in the array.
摘要翻译： NAND闪存系统被编程为在自增强期间具有最少的编程干扰和通过干扰，而不需要利用用于位线隔离的杂质注入，p阱偏置或位线偏置技术。将编程电压以多个短脉冲的形式施加到所选择的字线，同时将脉冲通过电压同时施加到未选择的字线，直到所选择的单元被编程。选择脉冲的持续时间和脉冲之间的时间以最小化未选择的单元，特别是所选字线上的未选择的单元的编程干扰，而不会引起阵列中的任何单元的通过干扰。

10. 发明授权

US06188606B1 Multi state sensing of NAND memory cells by varying source bias 有权
标题翻译：通过改变源偏置来对NAND存储器单元进行多状态感测
公开(公告)号：US06188606B1
公开(公告)日：2001-02-13
申请号：US09369600
申请日：1999-08-06
申请人： Narbeh Derhacobian , Hao Fang , Michael Han
发明人： Narbeh Derhacobian , Hao Fang , Michael Han
IPC分类号： G11C1604
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5642
摘要： A method and circuit for sensing multi states of a NAND memory cell by varying source bias, at a constant gate voltage, preferably zero volts, generating a memory cell current in response to the source bias, and sensing the memory cell state.
摘要翻译：一种用于通过在恒定栅极电压（优选为零伏特）下改变源偏置来感测NAND存储器单元的多状态的方法和电路，响应于源极偏置产生存储单元电流，并感测存储单元状态。

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