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1. 发明授权

US06467001B1 VLSI chip macro interface 失效
标题翻译： VLSI芯片宏接口
公开(公告)号：US06467001B1
公开(公告)日：2002-10-15
申请号：US09374222
申请日：1999-08-13
申请人： Mandy Alexander Gray , Michael J. Palmer , Ian David Judd
发明人： Mandy Alexander Gray , Michael J. Palmer , Ian David Judd
IPC分类号： G06F1336
CPC分类号： H04L49/101
摘要： The present invention provides a method and a system for connecting together, in a VLSI chip, a plurality of macros which require data flow connections between each other. A simple standard interface is realised between all macros. Any number of macros can be connected together, also allowing concurrent transactions between 4 or more macros using a cross-bar switch. Each macro may be a master (capable of requesting connections), a slave (capable of receiving connections from a master) or both. The centralised inter-connect logic includes three major components: the cross-bar switch, which makes the connections between the macros, the address decoder, which determines which slave each master wishes to connect to and an arbiter, which arbitrates between the macros when two or more masters request a connection simultaneously.
摘要翻译：本发明提供了一种用于在VLSI芯片中将需要相互数据流连接的多个宏连接在一起的方法和系统。所有宏之间实现简单的标准接口。任何数量的宏都可以连接在一起，也允许使用交叉开关的4个或更多宏之间的并发事务。每个宏可以是主（能够请求连接），从机（能够从主机接收连接）或两者。集中式互连逻辑包括三个主要部分：交叉开关，它们使得宏之间的连接，地址解码器确定每个主机希望连接的从属和仲裁器，它们在宏之间进行仲裁或更多的主人同时请求连接。

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