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1. 发明申请

WO2008128160A1 HEMTS BASED ON SI/NITRIDE STRUCTURES 审中-公开
标题翻译：基于SI / NITRIDE结构的HEMTS
公开(公告)号：WO2008128160A1
公开(公告)日：2008-10-23
申请号：PCT/US2008/060200
申请日：2008-04-14
申请人： MASSACHUSETTS INSTITUTE OF TECHNOLOGY , PALACIOS, Tomas , CHUNG, Jinwook
发明人： PALACIOS, Tomas , CHUNG, Jinwook
IPC分类号： H01L29/778 , H01L29/06 , H01L21/335
CPC分类号： H01L29/7787 , H01L29/0657 , H01L29/2003 , H01L29/66462
摘要： A transistor device includes a substrate. A buffer region is positioned on the substrate. A GaN/ AlGaN layer is positioned on the buffer region.
摘要翻译：晶体管器件包括衬底。缓冲区位于衬底上。 GaN / AlGaN层位于缓冲区上。

2. 发明申请

WO2010141351A3 WAFER BONDING TECHNIQUE IN NITRIDE SEMICONDUCTORS 审中-公开
公开(公告)号：WO2010141351A3
公开(公告)日：2010-12-09
申请号：PCT/US2010/036565
申请日：2010-05-28
申请人： MASSACHUSETTS INSTITUTE OF TECHNOLOGY , CHUNG, Jinwook , WANG, Han , PALACIOS, Tomas
发明人： CHUNG, Jinwook , WANG, Han , PALACIOS, Tomas
IPC分类号： H01L29/778 , H01L21/20 , B81B7/00
摘要： A semiconductor arrangement is provided that includes one or more substrate structures. One or more nitride-based material structures are used in fabricating nitride-based devices. One or more intermediary layers are interposed between the one or more substrate structures and the one or more nitride-based material structures. The one or more intermediary layers support the lattice mismatch and thermal expansion coefficients between the one or more nitride-based material structure and the one or more substrate structures. Several new electronic devices based on this arrangement are described.

3. 发明申请

WO2010042479A2 ENHANCEMENT-MODE NITRIDE TRANSISTOR 审中-公开
标题翻译：增强型氮化物晶体管
公开(公告)号：WO2010042479A2
公开(公告)日：2010-04-15
申请号：PCT/US2009/059646
申请日：2009-10-06
申请人： MASSACHUSETTS INSTITUTE OF TECHNOLOGY , LU, Bin , PALACIOS, Tomas
发明人： LU, Bin , PALACIOS, Tomas
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7788 , H01L29/2003 , H01L29/51 , H01L29/7787
摘要： A heterojunction for use in a transistor structure is provided. The heterojunction includes a barrier layer positioned beneath a gate region of the transistor structure. The barrier layer includes nitride-based semiconductor materials. A channel layer provides electrical conduction An intermediate layer near the barrier layer and including nitride-based semiconductor materials having a wider bandgap than the channel layer.
摘要翻译：提供了一种用于晶体管结构的异质结。异质结包括位于晶体管结构的栅极区域下方的势垒层。阻挡层包括氮化物基半导体材料。沟道层提供电传导在阻挡层附近的中间层，并且包括具有比沟道层更宽的带隙的氮化物基半导体材料。

4. 发明申请

WO2011100304A1 DUAL-GATE NORMALLY-OFF NITRIDE TRANSISTORS 审中-公开
标题翻译：双栅极正极氮化物晶体管
公开(公告)号：WO2011100304A1
公开(公告)日：2011-08-18
申请号：PCT/US2011/024168
申请日：2011-02-09
申请人： MASSACHUSETTS INSTITUTE OF TECHNOLOGY , LU, Bin , PALACIOS, Tomas
发明人： LU, Bin , PALACIOS, Tomas
IPC分类号： H01L29/778 , H01L29/423
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/42316 , H01L29/4236
摘要： A dual-gate normally-off nitride transistor that includes a first gate structure formed between a source electrode and a drain electrode for controlling a normally-off channel region of the dual-gate normally-off nitride transistor. A second gate structure is formed between the first gate structure and the drain electrode for modulating a normally-on channel region underneath the second gate structure. The magnitude of the threshold voltage of the second gate structure is smaller than the drain breakdown of the first gate structure for proper operation of the dual-gate normally-off nitride transistor.
摘要翻译：一种双栅极常关氮化物晶体管，其包括形成在源电极和漏电极之间的第一栅极结构，用于控制双栅极正常氮化物晶体管的常关沟道区。在第一栅极结构和漏极之间形成第二栅极结构，用于调制在第二栅极结构下方的常导通道区域。第二栅极结构的阈值电压的幅度小于用于双栅极常关氮化物晶体管的正常工作的第一栅极结构的漏极击穿。

5. 发明申请

WO2015102746A2 ELECTRONICS INCLUDING GRAPHENE-BASED HYBRID STRUCTURES 审中-公开
标题翻译：电子学包括基于石墨的混合结构
公开(公告)号：WO2015102746A2
公开(公告)日：2015-07-09
申请号：PCT/US2014/063903
申请日：2014-11-04
申请人： MASSACHUSETTS INSTITUTE OF TECHNOLOGY
发明人： YU, Lili , WANG, Han , PALACIOS, Tomas
IPC分类号： H01L29/43 , H01B1/04 , C01B31/04
CPC分类号： H01L29/45 , H01B1/04 , H01L21/28506 , H01L21/288 , H01L21/32055 , H01L21/3215 , H01L29/1606 , H01L29/413 , H01L29/454 , H01L29/456 , H01L29/786 , H01L29/861
摘要： Device are described that include a semiconductor material layer and at least one graphene-based electrode disposed over a portion of the semiconductor material layer, such that the at least one graphene-based electrode forms an overlap region with the semiconductor material layer. The device includes a means for providing charge carriers in the at least one graphene-based electrode proximate to the overlap region, to reduce a difference between a work function of the at least one graphene-based electrode and an electron affinity of the semiconductor material layer, to reduce a Schottky barrier height between the semiconductor material layer and the at least one graphene-based electrode.
摘要翻译：描述了包括半导体材料层和设置在半导体材料层的一部分上的至少一个基于石墨烯的电极的装置，使得至少一个基于石墨烯的电极与半导体材料层形成重叠区域。该器件包括用于在靠近重叠区域的至少一个基于石墨烯的电极中提供电荷载体的装置，以减少至少一个基于石墨烯的电极的功函数与半导体材料层的电子亲和力之间的差异以降低半导体材料层和至少一个基于石墨烯的电极之间的肖特基势垒高度。

6. 发明申请

WO2022212327A1 SEMICONDUCTOR DEVICE WITH ELECTRIC FIELD MANAGEMENT STRUCTURES 审中-公开
公开(公告)号：WO2022212327A1
公开(公告)日：2022-10-06
申请号：PCT/US2022/022285
申请日：2022-03-29
申请人： MASSACHUSETTS INSTITUTE OF TECHNOLOGY
发明人： PALACIOS, Tomas , ZUBAIR, Ahmad , NIROULA, John
IPC分类号： H01L29/70 , H01L29/739 , H01L21/762 , H01L29/772 , H01L29/778 , H01L29/861
摘要： A semiconductor device having an electric field management layer. The electric field management layer comprises a material with a relatively high dielectric constant that minimizes the risk of an electric field within the semiconductor device breaking down and damaging the semiconductor device.

7. 发明申请

WO2017100616A1 UNIVERSAL METHODOLOGY TO SYNTHESIZE DIVERSE TWO-DIMENSIONAL HETEROSTRUCTURES 审中-公开
标题翻译：综合多种二维异构结构的通用方法
公开(公告)号：WO2017100616A1
公开(公告)日：2017-06-15
申请号：PCT/US2016/065887
申请日：2016-12-09
申请人： MASSACHUSETTS INSTITUTE OF TECHNOLOGY
发明人： DRESSELHAUS, Mildred , KONG, Jing , PALACIOS, Tomas , LING, Xi , LI, Yuxuan
IPC分类号： H01L21/71 , H01L21/00 , H01L21/02 , H01L21/70 , H01L29/00 , H01L29/04
CPC分类号： H01L29/068 , H01L21/02112 , H01L21/0242 , H01L21/02422 , H01L21/02527 , H01L21/0254 , H01L21/02551 , H01L21/02568 , H01L21/0259 , H01L21/0262 , H01L21/02642 , H01L21/02645 , H01L21/8256 , H01L27/0207 , H01L27/088 , H01L29/0665 , H01L29/24 , H01L29/267 , H01L29/45 , H01L29/6603 , H01L29/778 , H01L29/861
摘要： A two-dimensional heterostructure is synthesized by producing a patterned first two- dimensional material on a growth substrate. The first two-dimensional material is patterned to define at least one void through which an exposed region of the growth substrate is exposed. Seed molecules are selectively deposited either on the exposed region of the growth substrate or on the patterned first two-dimensional material. A second two-dimensional material that is distinct from the first two-dimensional material is then grown from the deposited seed molecules.
摘要翻译：通过在生长衬底上产生图案化的第一二维材料来合成二维异质结构。第一二维材料被图案化以限定至少一个空隙，生长衬底的暴露区域通过该空隙暴露。种子分子选择性沉积在生长衬底的暴露区域上或图案化的第一二维材料上。然后从沉积的种子分子生长与第一种二维材料不同的第二种二维材料。

8. 发明申请

WO2007059220A2 METHODS TO SHAPE THE ELECTRIC FIELD IN ELECTRON DEVICES, PASSIVATE DISLOCATIONS AND POINT DEFECTS, AND ENHANCE THE LUMINESCENCE EFFICIENCY OF OPTICAL DEVICES 审中-公开
标题翻译：形成电子设备中的电场，钝化分离和点缺陷的方法，以及提高光器件的发光效率
公开(公告)号：WO2007059220A2
公开(公告)日：2007-05-24
申请号：PCT/US2006/044362
申请日：2006-11-15
申请人： THE REGENTS OF THE UNIVERSITY OF CALIFORNIA , PALACIOS, Tomas , SHEN, Likun , MISHRA, Umesh, K.
发明人： PALACIOS, Tomas , SHEN, Likun , MISHRA, Umesh, K.
IPC分类号： H01L29/739
CPC分类号： H01L29/2003 , H01L29/207 , H01L29/402 , H01L29/66462 , H01L29/7786 , H01L29/7787 , H01L33/0095
摘要： A fluorine treatment that can shape the electric field profile in electronic devices in 1, 2, or 3 dimensions is disclosed. A method to increase the breakdown voltage of AlGaN/GaN high electron mobility transistors, by the introduction of a controlled amount of dispersion into the device, is also disclosed. This dispersion is large enough to reduce the peak electric field in the channel, but low enough in order not to cause a significant decrease in the output power of the device. In this design, the whole transistor is passivated against dispersion with the exception of a small region 50 to 100 nm wide right next to the drain side of the gate. In that region, surface traps cause limited amounts of dispersion, that will spread the high electric field under the gate edge, therefore increasing the breakdown voltage. Three different methods to introduce dispersion in the 50 nm closest to the gate are described: (1) introduction of a small gap between the passivation and the gate metal, (2) gradually reducing the thickness of the passivation, and (3) gradually reducing the thickness of the AlGaN cap layer in the region close the gate.
摘要翻译：公开了可以在1,2或3维度的电子设备中形成电场分布的氟处理。还公开了通过将受控量的色散引入到器件中来增加AlGaN / GaN高电子迁移率晶体管的击穿电压的方法。该色散足够大以减少通道中的峰值电场，但是足够低以便不会导致器件的输出功率的显着降低。在这种设计中，整个晶体管对于色散是钝化的，除了在栅极的漏极侧旁边的50至100nm宽的小区域之外。在该区域中，表面陷阱引起有限量的色散，这将扩散栅极边缘处的高电场，从而增加击穿电压。描述了在最接近栅极的50nm中引入色散的三种不同的方法：（1）在钝化和栅极金属之间引入小间隙，（2）逐渐减小钝化的厚度，和（3）逐渐降低在关闭栅极的区域中的AlGaN盖层的厚度。

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