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1. 发明授权

US5631575A Intermediate voltage sensor for CMOS circuits 失效
标题翻译：用于CMOS电路的中压传感器
公开(公告)号：US5631575A
公开(公告)日：1997-05-20
申请号：US524848
申请日：1995-09-07
申请人： Kuen-Jong Lee , Jing-Jou Tang
发明人： Kuen-Jong Lee , Jing-Jou Tang
IPC分类号： G01R19/00 , H03K19/0948 , H03K19/00
CPC分类号： G01R19/0084
摘要： A built-in intermediate voltage sensor for CMOS circuits comprises a linear inverter, a first voltage control switch, a second voltage control switch, and a buffer. The linear inverter has an input end connected with an input signal under test. The first voltage control switch has a control end and an input end which are connected respectively with the input end and an output end of the linear inverter. The second voltage control switch has a control end and an input end which are connected respectively with the output end and the input end of the linear inverter. The buffer has an input end connected with the output end of the first voltage control switch and the output end of the second voltage control switch. The buffer gives forth an output voltage having a first logic value when the input signal has a voltage value of logic "0" or logic "1". The buffer is further capable of giving forth another output voltage having a second logic value when the input signal has a voltage value intermediate between logic "0" and logic "1".
摘要翻译：用于CMOS电路的内置中间电压传感器包括线性反相器，第一电压控制开关，第二电压控制开关和缓冲器。线性逆变器的输入端与被测输入信号相连。第一电压控制开关具有分别连接到线性逆变器的输入端和输出端的控制端和输入端。第二电压控制开关具有分别连接到线性逆变器的输出端和输入端的控制端和输入端。缓冲器具有与第一电压控制开关的输出端和第二电压控制开关的输出端连接的输入端。当输入信号具有逻辑“0”或逻辑“1”的电压值时，缓冲器提供具有第一逻辑值的输出电压。当输入信号具有介于逻辑“0”和逻辑“1”之间的电压值时，缓冲器还能够产生具有第二逻辑值的另一输出电压。

2. 发明授权

US5808476A Built-in current sensor for IDDQ monitoring 失效
标题翻译：内置电流传感器，用于IDDQ监控
公开(公告)号：US5808476A
公开(公告)日：1998-09-15
申请号：US688101
申请日：1996-07-29
申请人： Kuen-Jong Lee , Jing-Jou Tang
发明人： Kuen-Jong Lee , Jing-Jou Tang
IPC分类号： G01R31/30 , G01R31/26
CPC分类号： G01R31/3004 , G01R31/3008
摘要： An apparatus for measuring the current of a CMOS circuit includes a reference current generator to generate a reference current, a first current mirror to mirror the reference current, a second current mirror to mirror the current consumed by the CMOS circuit, an inverter to compare the above two mirrored currents and generate a signal to indicate which current is larger, and a multiplexer to switch between the normal circuit operation mode and the test mode. By this apparatus, it is possible to measure rapidly and accurately whether the CMOS circuit consumes an abnormally large current, thereby determining whether the CMOS circuit contains defects. This apparatus is based on the current-mode approach, hence can provide a high speed signal processing capability and has lower sensitivity to parameter deviation caused by process or operating temperature variations. It also provides scaleable sensing resolutions and programmable current reference.
摘要翻译：用于测量CMOS电路的电流的装置包括：产生参考电流的参考电流发生器，反映参考电流的第一电流镜;反映由CMOS电路消耗的电流的第二电流镜;反相器，用于比较高于两个镜像电流，并产生一个信号以指示哪个电流较大，以及多路复用器在正常电路操作模式和测试模式之间切换。通过该装置，可以快速准确地测量CMOS电路是否消耗异常大的电流，从而确定CMOS电路是否包含缺陷。该装置基于电流模式方式，因此可以提供高速信号处理能力，并且对由过程或工作温度变化引起的参数偏差具有较低的灵敏度。它还提供可扩展的感测分辨率和可编程电流参考。

3. 发明授权

US07159161B2 Test method and architecture for circuits having inputs 有权
标题翻译：具有输入电路的测试方法和结构
公开(公告)号：US07159161B2
公开(公告)日：2007-01-02
申请号：US10441691
申请日：2003-05-19
申请人： Kuen-Jong Lee , Jih-Jeen Chen , Cheng-Hua Huang
发明人： Kuen-Jong Lee , Jih-Jeen Chen , Cheng-Hua Huang
IPC分类号： G01R31/28
CPC分类号： G01R31/318563 , G01R31/318547 , G01R31/318583
摘要： A test method for a plurality of circuits respectively having inputs for greatly reducing the required test time and the control circuit complexity is provided. The method includes steps of providing a set of test patterns for detecting a characteristic of the circuits, providing a common data line, and electrically connecting the circuit inputs to the common data line so that the test pattern can be broadcasted to the circuits through the common data line. The present invention also provides an architecture for implementing such method.
摘要翻译：提供了分别具有用于大大减少所需测试时间和控制电路复杂度的输入的多个电路的测试方法。该方法包括以下步骤：提供用于检测电路的特性的一组测试图案，提供公共数据线，以及将电路输入电连接到公共数据线，使得测试图案可以通过公共广播到广播电路数据线。本发明还提供了一种用于实现这种方法的架构。

4. 发明授权

US07571414B2 Multi-project system-on-chip and its method 失效
标题翻译：多项目片上系统及其方法
公开(公告)号：US07571414B2
公开(公告)日：2009-08-04
申请号：US11453103
申请日：2006-06-15
申请人： Chun-Ming Huang , Chih-Chyau Yang , Jing-Yang Jou , Kuen-Jong Lee , Lan-Da Van
发明人： Chun-Ming Huang , Chih-Chyau Yang , Jing-Yang Jou , Kuen-Jong Lee , Lan-Da Van
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/66
摘要： A multi-project system-on-chip bench by integrating multiple system-on-chip projects into a chip, which uses a system chip bench, therefore, microprocessor, bus, embedded memory, peripheral component and input/output port is used together by those system-on-chip projects and the average cost of each system-on-chip is thus reduced. Moreover, this invention proposes a design method for multi-project system-on-chip bench, it let the user can effectively manage available data and verification environment in each design process flow hierarchy and in turn an easy-to-use design process flow is thus derived.
摘要翻译：通过将多个系统级芯片项目集成到一个使用系统芯片工作台的芯片上，因此微处理器，总线，嵌入式存储器，外设组件和输入/输出端口都集成在一起的多项目片上系统因此，这些系统级芯片项目和每个片上系统的平均成本因此降低。此外，本发明提出了一种多项目片上系统工作台的设计方法，使用户可以在每个设计流程层次上有效管理可用的数据和验证环境，从而简化设计过程流程从而得出。

5. 发明申请

US20070294658A1 Multi-project system-on-chip and its method 失效
标题翻译：多项目片上系统及其方法
公开(公告)号：US20070294658A1
公开(公告)日：2007-12-20
申请号：US11453103
申请日：2006-06-15
申请人： Chun-Ming Huang , Chih-Chyau Yang , Jing-Yang Jou , Kuen-Jong Lee , Lan-Da Van
发明人： Chun-Ming Huang , Chih-Chyau Yang , Jing-Yang Jou , Kuen-Jong Lee , Lan-Da Van
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/66
摘要： A multi-project system-on-chip bench by integrating multiple system-on-chip projects into a chip, which uses a system chip bench, therefore, microprocessor, bus, embedded memory, peripheral component and input/output port is used together by those system-on-chip projects and the average cost of each system-on-chip is thus reduced. Moreover, this invention proposes a design method for multi-project system-on-chip bench, it let the user can effectively manage available data and verification environment in each design process flow hierarchy and in turn an easy-to-use design process flow is thus derived.
摘要翻译：通过将多个系统级芯片项目集成到一个使用系统芯片工作台的芯片上，因此微处理器，总线，嵌入式存储器，外设组件和输入/输出端口都集成在一起的多项目片上系统因此，这些系统级芯片项目和每个片上系统的平均成本因此降低。此外，本发明提出了一种多项目片上系统工作台的设计方法，使用户可以在每个设计流程层次上有效管理可用的数据和验证环境，从而简化设计过程流程从而得出。

6. 发明授权

US06360342B1 Built-in self test for multiple memories in a chip 有权
标题翻译：内置自检芯片中的多个存储器
公开(公告)号：US06360342B1
公开(公告)日：2002-03-19
申请号：US09268666
申请日：1999-03-16
申请人： Kuen-Jong Lee , Jing-Yane Wu , Wen-Ben Jone
发明人： Kuen-Jong Lee , Jing-Yane Wu , Wen-Ben Jone
IPC分类号： G11C2900
CPC分类号： G11C29/40 , G11C29/14 , G11C29/26
摘要： A new built-in self-test architecture for multiple memories in a chip is proposed in the present invention. In this architecture, all memories under test are tested in parallel using only one address generator. When the address generated from the address generator exceeds one memory's address space the memory is turned off by a BIST controller. Each word in each memory is tested by a scan-in/out method. That is, the D flip-flops in the input and output ports of each memory are connected in series and form two scan chains, respectively. Only one data input and one data output are required for the scan chains of each memory. The outputs of all scan chains are connected to a self checker for fault analysis in parallel. The address generator, data generator, self checker and the test controller are all built in a chip to satisfy the requirement of built-in self-testing.
摘要翻译：本发明提出了一种用于芯片中的多个存储器的新的内置自检架构。在这种架构中，所有被测试的存储器只使用一个地址发生器并行测试。当地址发生器产生的地址超过一个存储器的地址空间时，BIST控制器关闭存储器。每个内存中的每个单词都通过扫描/输出方法进行测试。也就是说，每个存储器的输入和输出端口中的D触发器分别串联并形成两个扫描链。每个存储器的扫描链只需要一个数据输入和一个数据输出。所有扫描链的输出端连接到自检器并行进行故障分析。地址发生器，数据发生器，自检器和测试控制器都内置在芯片中，以满足内置自检的要求。

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