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1. 发明公开

US20240005777A1 Management Agent for Real-Time Interpretable Telemetry 审中-公开
公开(公告)号：US20240005777A1
公开(公告)日：2024-01-04
申请号：US18368480
申请日：2023-09-14
申请人： Kshitij Doshi , Mahesh Ketkar , Rahul Khanna , Muhammad Khellah , Ryan Kim , Mohan Kumar , Minh Le , Sten Sogaard , James Tschanz , Sriram Vangal
发明人： Kshitij Doshi , Mahesh Ketkar , Rahul Khanna , Muhammad Khellah , Ryan Kim , Mohan Kumar , Minh Le , Sten Sogaard , James Tschanz , Sriram Vangal
IPC分类号： G08C15/06
CPC分类号： G08C15/06
摘要： A controller of a processor core may select telemetry data generated by a plurality of sensors of the processor core at a first time interval of a plurality of time intervals. The controller may transform the telemetry data based at least in part on a model. The controller may detect a change at the first time interval based on the transformed telemetry data. The controller may determine an event based on the change. The controller may initiate an action during the first time interval based on the event.

2. 发明申请

US20060013067A1 Digital sounder module and method for detecting 有权
标题翻译：数字式发声器模块及其检测方法
公开(公告)号：US20060013067A1
公开(公告)日：2006-01-19
申请号：US11229634
申请日：2005-09-20
申请人： Sten Sogaard
发明人： Sten Sogaard
IPC分类号： G01S15/10
CPC分类号： G01S7/5273 , G01S7/529 , G01S15/96 , Y10S367/90
摘要： The invention is a digital sounder module and its method for detection. The digital sounder module includes a sonar carrier wave producing means, a band-pass filter, a pre-amplifier for providing a high sensitivity and extending a wide dynamic range, and an analog-to-digital converter for providing a digital implementation of a superheterodyne detector and producing an intermediate frequency. The digital sounder module also includes a programmable logic device for controlling a gain of the pre-amplifier and for digitally filtering the intermediate frequency and a microprocessor. The method implemented by the controlled per-amplifier gain processes the return echo signal by controlled ramp up of the gain over time to compensate for the change in signal strength in proportion to the length of the return path.
摘要翻译：本发明是数字式发声器模块及其检测方法。数字发声器模块包括声纳载波产生装置，带通滤波器，用于提供高灵敏度和扩展宽动态范围的前置放大器，以及用于提供超外差数字实现的模 - 数转换器检测器并产生中频。数字发声器模块还包括用于控制前置放大器的增益和用于数字滤波中频的可编程逻辑器件和微处理器。通过控制的每放大器增益实现的方法通过随着时间的增益的控制斜升来处理返回回波信号，以补偿与返回路径的长度成比例的信号强度的变化。

3. 发明授权

US08117512B2 Failure detection and mitigation in logic circuits 有权
标题翻译：逻辑电路中的故障检测和减轻
公开(公告)号：US08117512B2
公开(公告)日：2012-02-14
申请号：US12401559
申请日：2009-03-10
申请人： Steen Ditlev Sorensen , Sten Sogaard
发明人： Steen Ditlev Sorensen , Sten Sogaard
IPC分类号： G01R31/28 , H03M13/00 , G06F11/00
CPC分类号： A61B7/00 , A61B7/04
摘要： The present invention is directed to methods of monitoring logic circuits for failures. In particular, the methods are directed toward establishing parallel logic cores where failures are detected by comparing the parallel paths for equivalence at key locations by a redundancy checker. Any mismatch will result in a predetermined failsafe operational mode. In addition, important techniques are applied to periodically exercise individual parallel paths to ensure that logic cores are verified in a way that does not disturb any process being monitored or controlled. This feature is important in some industries, such as the nuclear power industry, where safety critical operations require a high state of reliability on logic circuit blocks which may be infrequently utilized.
摘要翻译：本发明涉及用于故障监视逻辑电路的方法。特别地，这些方法旨在建立并行逻辑核，其中通过冗余检查器比较关键位置处的等价的并行路径来检测故障。任何不匹配将导致预定的故障安全操作模式。此外，应用重要技术来周期性地执行单独的并行路径，以确保逻辑内核以不干扰被监视或控制的任何进程的方式被验证。这个特征在一些行业中是重要的，例如核电行业，其中安全关键操作需要在可能不常使用的逻辑电路块上的高可靠性。

4. 发明授权

US07870299B1 Advanced logic system 有权
标题翻译：先进的逻辑系统
公开(公告)号：US07870299B1
公开(公告)日：2011-01-11
申请号：US12026703
申请日：2008-02-06
申请人： Steen Ditlev Sorensen , Sten Sogaard
发明人： Steen Ditlev Sorensen , Sten Sogaard
IPC分类号： G06F3/00
CPC分类号： G06F11/1641 , G05B23/0291 , G05B2219/24054 , G05B2219/34334 , G06F11/0796 , G06F11/1004 , G06F11/1608 , G06F11/1616 , G06F11/2007 , G06F11/2015 , G06F11/27 , H04L12/40013 , H04L12/40176
摘要： The Advanced Logic System (ALS) is a complete control system architecture, based on a hardware platform rather than a software-based microprocessor system. It is significantly different from other PLC-type control system architectures, by implementing a FPGA in the central control unit. Standard FPGA logic circuits are used rather than a software-based microprocessor which eliminate problems with software based microprocessor systems, such as software common-mode failures. It provides a highly reliable system suitable for safety critical control systems, including nuclear plant protection systems. The system samples process inputs, provides for digital bus communications, applies a control logic function, and provides for controlled outputs. The architecture incorporates advanced features such as diagnostics, testability, and redundancy on multiple levels. It additionally provides significant improvements in failure detection, isolation, and mitigation for the highest level of integrity and reliability.
摘要翻译：高级逻辑系统（ALS）是一个基于硬件平台而不是基于软件的微处理器系统的完整的控制系统架构。通过在中央控制单元中实现FPGA，与其他PLC型控制系统架构有显着差异。使用标准FPGA逻辑电路而不是基于软件的微处理器，消除基于软件的微处理器系统的问题，例如软件共模故障。它提供了一个高度可靠的系统，适用于安全关键控制系统，包括核电站保护系统。系统采样过程输入，提供数字总线通信，应用控制逻辑功能，并提供受控输出。该架构结合了多个级别的高级功能，如诊断，可测试性和冗余度。它还提供了故障检测，隔离和缓解方面的显着改进，以实现最高级别的完整性和可靠性。

5. 发明授权

US08554953B1 Advanced logic system diagnostics and monitoring 有权
标题翻译：先进的逻辑系统诊断和监控
公开(公告)号：US08554953B1
公开(公告)日：2013-10-08
申请号：US12914737
申请日：2010-10-28
申请人： Steen Ditlev Sorensen , Sten Sogaard
发明人： Steen Ditlev Sorensen , Sten Sogaard
IPC分类号： G06F3/00
CPC分类号： A61B7/04 , A61B7/00
摘要： The Advanced Logic System (ALS) is a complete control system architecture, based on a hardware platform rather than a software-based microprocessor system. It is significantly different from other PLC-type control system architectures, by implementing a FPGA in the central control unit. Standard FPGA logic circuits are used rather than a software-based microprocessor which eliminate problems with software based microprocessor systems, such as software common-mode failures. It provides a highly reliable system suitable for safety critical control systems, including nuclear plant protection systems. The system samples process inputs, provides for digital bus communications, applies a control logic function, and provides for controlled outputs. The architecture incorporates advanced features such as diagnostics, testability, and redundancy on multiple levels. It additionally provides significant improvements in failure detection, isolation, and mitigation for the highest level of integrity and reliability.
摘要翻译：高级逻辑系统（ALS）是一个基于硬件平台而不是基于软件的微处理器系统的完整的控制系统架构。通过在中央控制单元中实现FPGA，与其他PLC型控制系统架构显着不同。使用标准FPGA逻辑电路而不是基于软件的微处理器，消除基于软件的微处理器系统的问题，例如软件共模故障。它提供了一个高度可靠的系统，适用于安全关键控制系统，包括核电站保护系统。系统采样过程输入，提供数字总线通信，应用控制逻辑功能，并提供受控输出。该架构结合了多个级别的高级功能，如诊断，可测试性和冗余度。它还提供了故障检测，隔离和缓解方面的显着改进，以实现最高级别的完整性和可靠性。

6. 发明授权

US07106657B2 Digital sounder module and method for detecting 有权
公开(公告)号：US07106657B2
公开(公告)日：2006-09-12
申请号：US11229634
申请日：2005-09-20
申请人： Sten Sogaard
发明人： Sten Sogaard
IPC分类号： G01S15/96 , G01S15/00
CPC分类号： G01S7/5273 , G01S7/529 , G01S15/96 , Y10S367/90
摘要： The invention is a digital sounder module and its method for detection. The digital sounder module includes a sonar carrier wave producing means, a band-pass filter, a pre-amplifier for providing a high sensitivity and extending a wide dynamic range, and an analog-to-digital converter for providing a digital implementation of a superheterodyne detector and producing an intermediate frequency. The digital sounder module also includes a programmable logic device for controlling a gain of the pre-amplifier and for digitally filtering the intermediate frequency and a microprocessor. The method implemented by the controlled per-amplifier gain processes the return echo signal by controlled ramp up of the gain over time to compensate for the change in signal strength in proportion to the length of the return path.

7. 发明授权

US08156251B1 Advanced logic system 有权
标题翻译：先进的逻辑系统
公开(公告)号：US08156251B1
公开(公告)日：2012-04-10
申请号：US12914724
申请日：2010-10-28
申请人： Steen Ditlev Sorensen , Sten Sogaard
发明人： Steen Ditlev Sorensen , Sten Sogaard
IPC分类号： G06F3/00
CPC分类号： G06F11/1641 , G05B23/0291 , G05B2219/24054 , G05B2219/34334 , G06F11/0796 , G06F11/1004 , G06F11/1608 , G06F11/1616 , G06F11/2007 , G06F11/2015 , G06F11/27 , H04L12/40013 , H04L12/40176
摘要： The Advanced Logic System (ALS) is a complete control system architecture, based on a hardware platform rather than a software-based microprocessor system. It is significantly different from other PLC-type control system architectures, by implementing a FPGA in the central control unit. Standard FPGA logic circuits are used rather than a software-based microprocessor which eliminate problems with software based microprocessor systems, such as software common-mode failures. It provides a highly reliable system suitable for safety critical control systems, including nuclear plant protection systems. The system samples process inputs, provides for digital bus communications, applies a control logic function, and provides for controlled outputs. The architecture incorporates advanced features such as diagnostics, testability, and redundancy on multiple levels. It additionally provides significant improvements in failure detection, isolation, and mitigation for the highest level of integrity and reliability.
摘要翻译：高级逻辑系统（ALS）是一个基于硬件平台而不是基于软件的微处理器系统的完整的控制系统架构。通过在中央控制单元中实现FPGA，与其他PLC型控制系统架构显着不同。使用标准FPGA逻辑电路而不是基于软件的微处理器，消除基于软件的微处理器系统的问题，例如软件共模故障。它提供了一个高度可靠的系统，适用于安全关键控制系统，包括核电站保护系统。系统采样过程输入，提供数字总线通信，应用控制逻辑功能，并提供受控输出。该架构结合了多个级别的高级功能，如诊断，可测试性和冗余度。它还提供了故障检测，隔离和缓解方面的显着改进，以实现最高级别的完整性和可靠性。

8. 发明申请

US20110209021A1 Failure Detection and Mitigation in Logic Circuits 有权
标题翻译：逻辑电路中的故障检测和减轻
公开(公告)号：US20110209021A1
公开(公告)日：2011-08-25
申请号：US12401559
申请日：2009-03-10
申请人： Steen Ditlev Sorensen , Sten Sogaard
发明人： Steen Ditlev Sorensen , Sten Sogaard
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： A61B7/00 , A61B7/04
摘要： The present invention is directed to methods of monitoring logic circuits for failures. In particular, the methods are directed toward establishing parallel logic cores where failures are detected by comparing the parallel paths for equivalence at key locations by a redundancy checker. Any mismatch will result in a predetermined failsafe operational mode. In addition, important techniques are applied to periodically exercise individual parallel paths to ensure that logic cores are verified in a way that does not disturb any process being monitored or controlled. This feature is important in some industries, such as the nuclear power industry, where safety critical operations require a high state of reliability on logic circuit blocks which may be infrequently utilized.
摘要翻译：本发明涉及用于故障监视逻辑电路的方法。特别地，这些方法旨在建立并行逻辑核，其中通过冗余检查器比较关键位置处的等价的并行路径来检测故障。任何不匹配将导致预定的故障安全操作模式。此外，应用重要技术来周期性地执行单独的并行路径，以确保逻辑内核以不干扰被监视或控制的任何进程的方式被验证。这个特征在一些行业中是重要的，例如核电行业，其中安全关键操作需要在可能不常使用的逻辑电路块上的高可靠性。

9. 发明授权

US06950372B2 Digital sounder module and method for detecting 有权
标题翻译：数字式发声器模块及其检测方法
公开(公告)号：US06950372B2
公开(公告)日：2005-09-27
申请号：US10704606
申请日：2003-11-12
申请人： Sten Sogaard
发明人： Sten Sogaard
IPC分类号： G01S15/10 , G01S7/526 , G01S7/527 , G01S7/529 , G01S15/96 , G01S15/00
CPC分类号： G01S7/5273 , G01S7/529 , G01S15/96 , Y10S367/90
摘要： The invention is a digital sounder module and its method for detection. The digital sounder module includes a sonar carrier wave producing means, a band-pass filter, a pre-amplifier for providing a high sensitivity and extending a wide dynamic range, and an analog-to-digital converter for providing a digital implementation of a superheterodyne detector and producing an intermediate frequency. The digital sounder module also includes a programmable logic device for controlling a gain of the pre-amplifier and for digitally filtering the intermediate frequency and a microprocessor. The method implemented by the controlled per-amplifier gain processes the return echo signal by controlled ramp up of the gain over time to compensate for the change in signal strength in proportion to the length of the return path.
摘要翻译：本发明是数字式发声器模块及其检测方法。数字发声器模块包括声纳载波产生装置，带通滤波器，用于提供高灵敏度和扩展宽动态范围的前置放大器，以及用于提供超外差数字实现的模 - 数转换器检测器并产生中频。数字发声器模块还包括用于控制前置放大器的增益和用于数字滤波中频的可编程逻辑器件和微处理器。通过控制的每放大器增益实现的方法通过随着时间的增益的控制斜升来处理返回回波信号，以补偿与返回路径的长度成比例的信号强度的变化。

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