专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060096305A1 Fluid flowmeter and engine control system using the same 审中-公开
标题翻译：流体流量计和发动机控制系统使用相同
公开(公告)号：US20060096305A1
公开(公告)日：2006-05-11
申请号：US11206733
申请日：2005-08-19
申请人： Keiji Hanzawa , Masahiro Matsumoto , Hiromichi Yamada , Hiroshi Nakano , Hiroyasu Sukesako
发明人： Keiji Hanzawa , Masahiro Matsumoto , Hiromichi Yamada , Hiroshi Nakano , Hiroyasu Sukesako
IPC分类号： F25B39/04
CPC分类号： G01F1/6845 , G01F1/696 , G01F1/6986 , G01F1/699
摘要： An air temperature sensor sensing an air temperature, supplied with a pulse signal as a driving signal from a pulse signal source, senses an air temperature based on the pulse signal. While the air temperature sensor is self-heated during an electrical current supplying time period by the pulse signal, it is cooled during an electrical current halting time period. Accordingly, the self-heating of the air temperature sensor by the driving signal is suppressed, and a thermal effect on air flow rate sensing elements disposed in an air flow downstream side of the air temperature sensor is also reduced.
摘要翻译：感测从脉冲信号源提供脉冲信号作为驱动信号的空气温度的空气温度传感器基于脉冲信号感测空气温度。当通过脉冲信号在空气温度传感器在电流供应时间段内自加热时，在电流停止时间段期间，其被冷却。因此，通过驱动信号来抑制空气温度传感器的自身加热，并且对于设置在空气温度传感器的空气流下游侧的空气流量感测元件的热效应也降低。

2. 发明授权

US07260657B2 Serial data transferring apparatus 有权
标题翻译：串行数据传输设备
公开(公告)号：US07260657B2
公开(公告)日：2007-08-21
申请号：US10491285
申请日：2001-10-02
申请人： Masahiro Matsumoto , Fumio Murabayashi , Hiromichi Yamada , Keiji Hanzawa , Hiroyasu Sukesako
发明人： Masahiro Matsumoto , Fumio Murabayashi , Hiromichi Yamada , Keiji Hanzawa , Hiroyasu Sukesako
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： H04L7/10 , H04J3/24 , H04J7/00 , H04L7/046 , H04L7/06
摘要： A master unit sends a start signal to a slave unit. When receiving the start signal from the master unit, the slave unit sends, to the master unit, a synchronization field that is a data train (pulse signal) indicative of a transfer clock with which the slave unit is able to perform transferring and receiving operations. The master unit sends, to the slave unit, command data in accordance with the transfer clock indicated by the synchronization field sent from the slave unit. In response to the command data sent from the master unit, the slave unit sends, to the master unit, response data in accordance with the transfer clock indicated by the synchronization field. Thus, in a communication system employing a serial data transferring apparatus of the present invention, the master unit establishes the synchronization for the data transfer, while the slave unit is free from a burden of establishing the synchronization for the data transfer. A serial data transferring apparatus is realized which can simplify the structure of the slave unit, cut the total cost, and reduce noise.
摘要翻译：主单元向从单元发送启动信号。当从主单元接收到起始信号时，从单元向主单元发送同步字段，该同步字段是指示从单元能够执行传送和接收操作的传送时钟的数据串（脉冲信号）。主单元根据从从单元发送的同步字段指示的传送时钟向从属单元发送命令数据。响应于从主单元发送的命令数据，从单元根据由同步字段指示的传送时钟向主单元发送响应数据。因此，在采用本发明的串行数据传送装置的通信系统中，主单元建立用于数据传送的同步，而从单元没有建立用于数据传送的同步的负担。实现了串行数据传送装置，其可以简化从单元的结构，降低总成本并降低噪声。

3. 发明申请

US20050091428A1 Serial data transferring apparatus 有权
标题翻译：串行数据传输设备
公开(公告)号：US20050091428A1
公开(公告)日：2005-04-28
申请号：US10491285
申请日：2001-10-02
申请人： Masahiro Matsumoto , Fumio Murabayashi , Hiromichi Yamada , Keiji Hanzawa , Hiroyasu Sukesako
发明人： Masahiro Matsumoto , Fumio Murabayashi , Hiromichi Yamada , Keiji Hanzawa , Hiroyasu Sukesako
IPC分类号： H04L7/02 , H04L7/04 , H04L7/06 , H04L7/10 , G06F3/00
CPC分类号： H04L7/10 , H04J3/24 , H04J7/00 , H04L7/046 , H04L7/06
摘要： A master unit sends a start signal to a slave unit. When receiving the start signal from the master unit, the slave unit sends, to the master unit, a synchronization field that is a data train (pulse signal) indicative of a transfer clock with which the slave unit is able to perform transferring and receiving operations. The master unit sends, to the slave unit, command data in accordance with the transfer clock indicated by the synchronization field sent from the slave unit. In response to the command data sent from the master unit, the slave unit sends, to the master unit, response data in accordance with the transfer clock indicated by the synchronization field. Thus, in a communication system employing a serial data transferring apparatus of the present invention, the master unit establishes the synchronization for the data transfer, while the slave unit is free from a burden of establishing the synchronization for the data transfer. A serial data transferring apparatus is realized which can simplify the structure of the slave unit, cut the total cost, and reduce noise.
摘要翻译：主单元向从单元发送启动信号。当从主单元接收到起始信号时，从单元向主单元发送同步字段，该同步字段是指示从单元能够执行传送和接收操作的传送时钟的数据串（脉冲信号）。主单元根据从从单元发送的同步字段指示的传送时钟向从属单元发送命令数据。响应于从主单元发送的命令数据，从单元根据由同步字段指示的传送时钟向主单元发送响应数据。因此，在采用本发明的串行数据传送装置的通信系统中，主单元建立用于数据传送的同步，而从单元没有建立用于数据传送的同步的负担。实现了串行数据传送装置，其可以简化从单元的结构，降低总成本并降低噪声。

4. 发明授权

US06539322B1 Sensor device 有权
标题翻译：传感器装置
公开(公告)号：US06539322B1
公开(公告)日：2003-03-25
申请号：US09583770
申请日：2000-05-31
申请人： Masahiro Matsumoto , Kohei Sakurai , Fumio Murabayashi , Hiromichi Yamada , Tatsumi Yamauchi , Atsushi Miyazaki , Keiji Hanzawa
发明人： Masahiro Matsumoto , Kohei Sakurai , Fumio Murabayashi , Hiromichi Yamada , Tatsumi Yamauchi , Atsushi Miyazaki , Keiji Hanzawa
IPC分类号： G06M1102
CPC分类号： G01D3/08 , G01D3/022 , Y10T436/11
摘要： A sensor device is provided which included a digital arithmetic processing unit which performs arithmetic processing through a program stored therein in advance, a pulse generator for generating pulses through the program, and a unit for causing the output voltage of the sensor device to stay at either a power source voltage concerned or the ground voltage, when the pulses from the pulse generator are interrupted, thereby, a sensor device using digital arithmetic processing and outputting analogue voltages is provided allowing the host system to judge easily whether the sensor device is operating normally or is failing.
摘要翻译：提供了一种传感器装置，其包括：数字运算处理单元，其预先通过存储在其中的程序执行算术处理;脉冲发生器，用于通过程序产生脉冲;以及单元，用于使传感器装置的输出电压停留在任一个当来自脉冲发生器的脉冲被中断时，提供有关的电源电压或接地电压，由此提供使用数字运算处理和输出模拟电压的传感器装置，允许主机系统容易地判断传感器装置是否正常运行，或者失败了

5. 发明授权

US06282136B1 Semiconductor memory devices and sensors using the same 失效
标题翻译：半导体存储器件和使用其的传感器
公开(公告)号：US06282136B1
公开(公告)日：2001-08-28
申请号：US09578854
申请日：2000-05-26
申请人： Kohei Sakurai , Tatsumi Yamauchi , Masahiro Matsumoto , Fumio Murabayashi , Hiromichi Yamada , Atsushi Miyazaki , Keiji Hanzawa
发明人： Kohei Sakurai , Tatsumi Yamauchi , Masahiro Matsumoto , Fumio Murabayashi , Hiromichi Yamada , Atsushi Miyazaki , Keiji Hanzawa
IPC分类号： G11C700
CPC分类号： G11C7/1072 , G11C7/12 , G11C8/00
摘要： In a semiconductor memory device, the drain of a transistor for pre-charging is connected to a data line via the Y switch. Lower level bit signals are input into an X decoder for selecting the word line in a memory cell array; and higher level bit signals are input into a Y decoder for selecting the Y switch control signal lines. The addresses in the memory cell array are arranged sequentially in the direction of the data lines.
摘要翻译：在半导体存储器件中，用于预充电的晶体管的漏极经由Y开关连接到数据线。低电平位信号被输入到用于选择存储单元阵列中的字线的X解码器中; 并且较高电平位信号被输入到用于选择Y开关控制信号线的Y解码器中。存储单元阵列中的地址在数据线的方向上顺序排列。

6. 发明授权

US06538866B1 Circuit for protecting a load from an overvoltage 失效
标题翻译：用于保护负载免受过电压的电路
公开(公告)号：US06538866B1
公开(公告)日：2003-03-25
申请号：US09526737
申请日：2000-03-16
申请人： Keiji Hanzawa , Masahiro Matsumoto , Fumio Murabayashi , Tatsumi Yamauchi , Hiromichi Yamada , Kohei Sakurai , Atsushi Miyazaki
发明人： Keiji Hanzawa , Masahiro Matsumoto , Fumio Murabayashi , Tatsumi Yamauchi , Hiromichi Yamada , Kohei Sakurai , Atsushi Miyazaki
IPC分类号： H02H900
CPC分类号： H01L27/0251 , H02H9/04
摘要： A circuit for protecting a load from an overvoltage can be integrated together with the load on the same chip by an MOS transistor manufacture process. This overvoltage protecting circuit is composed of a surge protection circuit, an overvoltage detecting circuit and a switching circuit. The surge protection circuit including two MOS transistors operates so that a surge voltage applied to a power supply receiving terminal is clamped by virtue of the source-drain breakdown voltage of the two MOS transistors, thereby absorbing the surge energy. The overvoltage detecting circuit including two MOS transistors operates so that a DC voltage supplied from the surge protection circuit is monitored with the source-drain voltage of the two MOS transistors taken as a reference voltage, thereby detecting an overvoltage. An overvoltage detection output brings an MOS transistor of the switching circuit into a turned-off condition to protect the load.
摘要翻译：可以通过MOS晶体管制造工艺将用于保护负载的过电压的电路与负载集成在同一芯片上。该过电压保护电路由浪涌保护电路，过电压检测电路和开关电路构成。包括两个MOS晶体管的浪涌保护电路工作，借助于两个MOS晶体管的源极 - 漏极击穿电压来钳位施加到电源接收端的浪涌电压，从而吸收浪涌能量。包括两个MOS晶体管的过电压检测电路进行工作，从而以两个MOS晶体管的源极 - 漏极电压作为参考电压来监视从浪涌保护电路提供的直流电压，从而检测过电压。过电压检测输出使开关电路的MOS晶体管成为关断状态，以保护负载。

7. 发明授权

US08639905B2 Microcontroller and electronic control unit 有权
标题翻译：微控制器和电子控制单元
公开(公告)号：US08639905B2
公开(公告)日：2014-01-28
申请号：US13614313
申请日：2012-09-13
申请人： Hiromichi Yamada , Yuichi Ishiguro , Nobuyasu Kanekawa
发明人： Hiromichi Yamada , Yuichi Ishiguro , Nobuyasu Kanekawa
IPC分类号： G06F12/02
CPC分类号： G06F11/1641 , G06F11/1683
摘要： A microcontroller in which respective CPUs execute different applications so as to improve processing performance, and the respective CPUs execute an application that requires safety and mutually compare the results thereof so as to enhance the reliability of write data is provided. The microcontroller has a plurality of processing systems made up of a first CPU, a second CPU, a first memory and a second memory, and for the instruction processing about specific processing set in advance, the write to peripheral modules which are not multiplexed is executed twice, and the write data of the first time and the second time are mutually collated.
摘要翻译：其中相应CPU执行不同应用以提高处理性能的微控制器，并且相应的CPU执行需要安全性并相互比较其结果的应用，以提供写入数据的可靠性。微控制器具有由第一CPU，第二CPU，第一存储器和第二存储器构成的多个处理系统，并且对于关于预先设定的特定处理的指令处理，执行未复用的对外围模块的写入两次，并且第一次和第二次的写入数据被相互整理。

8. 发明申请

US20070180317A1 ERROR CORRECTION METHOD 有权
标题翻译：错误校正方法
公开(公告)号：US20070180317A1
公开(公告)日：2007-08-02
申请号：US11623441
申请日：2007-01-16
申请人： Teppei HIROTSU , Hiromichi Yamada , Teruaki Sakata , Kesami Hagiwara
发明人： Teppei HIROTSU , Hiromichi Yamada , Teruaki Sakata , Kesami Hagiwara
IPC分类号： G06F11/00
CPC分类号： G06F11/1407
摘要： This method is an error correction method such that, when an error is detected in a CPU with pipeline struct, a content of a register file is restored by a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error, and a rollback control that re-executes an instruction from the [Instruction N+1] which is the next instruction of the [Instruction N] is performed. The method collects a parity check result of arbitrary Flip-Flops existing inside the CPU, and detects an error. As a result, the content of the register file is restored into the instruction execute completion state preceding to the instruction range likely to malfunction by the error, and the instruction can be roll backed from the beginning of the instruction range likely having malfunctioned by the error.
摘要翻译：该方法是一种错误校正方法，使得当在具有流水线结构的CPU中检测到错误时，通过延迟的寄存器文件来恢复寄存器文件的内容，该延迟寄存器文件保持在之前正确执行的[指令N]的执行完成状态该错误和执行作为[指令N]的下一条指令的[指令N + 1]的指令的回滚控制。该方法收集CPU内存在的任意Flip-Flops的奇偶校验结果，并检测出错误。结果，寄存器文件的内容被恢复到可能由错误导致故障的指令范围之前的指令执行完成状态，并且可以从可能由错误发生故障的指令范围的开始滚转指令。

9. 发明授权

US06915413B2 Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein 失效
公开(公告)号：US06915413B2
公开(公告)日：2005-07-05
申请号：US10101480
申请日：2002-03-20
申请人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
发明人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
IPC分类号： G06F9/30 , G06F9/318 , G06F9/32 , G06F7/36 , G06F9/45 , G06F17/30
CPC分类号： G06F9/30178 , Y10S707/99942
摘要： A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.

10. 发明申请

US20050040978A1 A/D converter and a microcontroller including the same 有权
标题翻译： A / D转换器和包含它的微控制器
公开(公告)号：US20050040978A1
公开(公告)日：2005-02-24
申请号：US10912542
申请日：2004-08-06
申请人： Yuichiro Morita , Kohei Sakurai , Nobuyasu Kanekawa , Masatoshi Hoshino , Hiromichi Yamada , Kotaro Shimamura , Satoshi Tanaka , Naoki Yada
发明人： Yuichiro Morita , Kohei Sakurai , Nobuyasu Kanekawa , Masatoshi Hoshino , Hiromichi Yamada , Kotaro Shimamura , Satoshi Tanaka , Naoki Yada
IPC分类号： H03M1/00 , H03M1/12
CPC分类号： H03M1/1225
摘要： In an A/D converter and a microcontroller including the same, the number of selection patterns of analog input channels is increased for each A/D conversion and the A/D conversion is conducted using an A/D converter having only fundamental functions without imposing load onto a CPU. The A/D converter or a DMA transfer device includes an A/D conversion table including one or more entries. Each entry includes enable bits for setting whether or not an A/D conversion is executed for the respective analog input channels and a plurality of count number bits for setting a number of executions of the A/D conversion.
摘要翻译：在A / D转换器和包含该A / D转换器的微控制器中，对于每个A / D转换，模拟输入通道的选择模式的数量增加，并且使用仅具有基本功能的A / D转换器进行A / D转换，而不施加加载到CPU上 A / D转换器或DMA传输装置包括包括一个或多个条目的A / D转换表。每个条目包括用于设置是否对各个模拟输入通道执行A / D转换的使能位以及用于设置A / D转换执行次数的多个计数号位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式