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1. 发明申请

US20100031055A1 EMBEDDED DEVICE HAVING COUNTERMEASURE FUNCTION AGAINST FAULT ATTACK 有权
标题翻译：具有防止故障攻击的计数功能的嵌入式设备
公开(公告)号：US20100031055A1
公开(公告)日：2010-02-04
申请号：US12560222
申请日：2009-09-15
申请人： Kazuyoshi Furukawa , Kouichi Itoh , Masahiko Takenaka
发明人： Kazuyoshi Furukawa , Kouichi Itoh , Masahiko Takenaka
IPC分类号： H04L9/00 , H04L9/28 , G06F7/38
CPC分类号： G06F7/723 , G06F7/728 , G06F2207/7271 , H04L9/004 , H04L9/302 , H04L9/3066
摘要： A cryptographic processing device, comprising: a storage unit; initial setting unit for setting a value to be stored in the storage unit; Montgomery modular multiplication operation unit for performing a Montgomery modular multiplication operation plural times for a value set by the initial setting unit; and fault attack detection unit for determining whether or not a fault attack occurred for each of at least some parts of the Montgomery modular multiplication operations performed plural times.
摘要翻译：一种加密处理装置，包括：存储单元; 初始设定单元，用于设定存储在存储单元中的值; 蒙哥马利乘法运算单元，用于对由初始设定单元设定的值进行多次蒙哥马利乘法运算; 以及故障攻击检测单元，用于确定多次执行的蒙哥马利乘法运算的至少一些部分中是否发生故障攻击。

2. 发明申请

US20100023571A1 Modular multiplication calculation apparatus used for Montgomery method 有权
标题翻译：用于蒙哥马利方法的模块化乘法计算装置
公开(公告)号：US20100023571A1
公开(公告)日：2010-01-28
申请号：US12218060
申请日：2008-07-11
申请人： Kazuyoshi Furukawa , Masahiko Takenaka
发明人： Kazuyoshi Furukawa , Masahiko Takenaka
IPC分类号： G06F7/38
CPC分类号： G06F7/728
摘要： REDC (A*B) is calculated for the values A and B by using a Montgomery's algorithm REDC. The part related to the A*B is performed by the three-input two-output product-sum calculation circuit. One digit ai of the value A, one digit bj of the value B and a carry value c1 are input to the product-sum calculation circuit, and ai*bj+c1 is calculated thereat. The higher-order digit of the r-adic two-digit of the calculation result is used as the carry value c1, and the lower digit is used for a later calculation. Further, one digit ni of a modulo N for the REDC, a predetermined value m and a carry value c2 are input into the product-sum calculation circuit, and n*ni+c2 is calculated thereat. The higher-order digit is used as the carry value c2, and the lower digit is used for a later calculation.
摘要翻译：通过使用蒙哥马利的算法REDC计算值A和B的REDC（A * B）。与A * B相关的部分由三输入双输出积和计算电路进行。值A的一位数ai，值B的一位数bj和进位值c1被输入到乘积和计算电路，并且计算ai * bj + c1。将计算结果的r-adic两位数的高阶数字用作进位值c1，将下位数用于后续计算。此外，对于REDC，模N的一位数ni，预定值m和进位值c2被输入到乘积和计算电路中，并且在那里计算n * ni + c2。高位数字用作进位值c2，下位数用于后续计算。

3. 发明授权

US08707057B2 Data processing apparatus and data processing method 有权
标题翻译：数据处理装置及数据处理方法
公开(公告)号：US08707057B2
公开(公告)日：2014-04-22
申请号：US13237317
申请日：2011-09-20
申请人： Kazuyoshi Furukawa , Takeshi Shimoyama , Masahiko Takenaka
发明人： Kazuyoshi Furukawa , Takeshi Shimoyama , Masahiko Takenaka
IPC分类号： G06F11/30 , G06F12/14
CPC分类号： H04L9/002 , H04L9/06 , H04L2209/12
摘要： A data processing apparatus includes an address bus, a scramble unit, and a data bus. The address bus outputs address data to be given to a memory apparatus. The scramble unit scrambles write-in data into a storage position in the memory apparatus identified by the address data to obtain confidential data. The data bus outputs the confidential data. The scramble unit includes a first scrambler, a first converter and a second scrambler. The first scrambler XORs first mask data corresponding to the address data and the write-in data for each bit and makes it first scrambled data. The first converter performs one-to-one substitution conversion of the first scrambled data. The second scrambler XORs second mask data corresponding to the address data and data after the conversion of the first scrambled data by the first converter and outputs obtained second scrambled data as the confidential data.
摘要翻译：数据处理装置包括地址总线，加扰单元和数据总线。地址总线输出要提供给存储装置的地址数据。加扰单元将写入数据加密到由地址数据识别的存储装置中的存储位置，以获得机密数据。数据总线输出机密数据。加扰单元包括第一加扰器，第一转换器和第二加扰器。第一加扰器将对应于地址数据的第一掩码数据和每个位的写入数据进行异或，并使其成为第一个加扰数据。第一转换器执行第一加扰数据的一对一替换转换。第二加扰器将对应于地址数据的第二掩码数据和由第一转换器转换第一加扰数据之后的数据进行异或，并将获得的第二加密数据作为机密数据输出。

4. 发明授权

US08327156B2 Embedded device having countermeasure function against fault attack 有权
标题翻译：嵌入式设备具有防故障攻击的对策功能
公开(公告)号：US08327156B2
公开(公告)日：2012-12-04
申请号：US12560222
申请日：2009-09-15
申请人： Kazuyoshi Furukawa , Kouichi Itoh , Masahiko Takenaka
发明人： Kazuyoshi Furukawa , Kouichi Itoh , Masahiko Takenaka
IPC分类号： G06F21/00
CPC分类号： G06F7/723 , G06F7/728 , G06F2207/7271 , H04L9/004 , H04L9/302 , H04L9/3066
摘要： A cryptographic processing device, comprising: a storage unit; initial setting unit for setting a value to be stored in the storage unit; Montgomery modular multiplication operation unit for performing a Montgomery modular multiplication operation plural times for a value set by the initial setting unit; and fault attack detection unit for determining whether or not a fault attack occurred for each of at least some parts of the Montgomery modular multiplication operations performed plural times.
摘要翻译：一种加密处理装置，包括：存储单元; 初始设定单元，用于设定存储在存储单元中的值; 蒙哥马利乘法运算单元，用于对由初始设定单元设定的值进行多次蒙哥马利乘法运算; 以及故障攻击检测单元，用于确定多次执行的蒙哥马利乘法运算的至少一些部分中是否发生故障攻击。

5. 发明申请

US20120008782A1 DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD 有权
标题翻译：数据处理设备和数据处理方法
公开(公告)号：US20120008782A1
公开(公告)日：2012-01-12
申请号：US13237317
申请日：2011-09-20
申请人： Kazuyoshi FURUKAWA , Takeshi Shimoyama , Masahiko Takenaka
发明人： Kazuyoshi FURUKAWA , Takeshi Shimoyama , Masahiko Takenaka
IPC分类号： H04L9/20
CPC分类号： H04L9/002 , H04L9/06 , H04L2209/12
摘要： A data processing apparatus includes an address bus, a scramble unit, and a data bus. The address bus outputs address data to be given to a memory apparatus. The scramble unit scrambles write-in data into a storage position in the memory apparatus identified by the address data to obtain confidential data. The data bus outputs the confidential data. The scramble unit includes a first scrambler, a first converter and a second scrambler. The first scrambler XORs first mask data corresponding to the address data and the write-in data for each bit and makes it first scrambled data. The first converter performs one-to-one substitution conversion of the first scrambled data. The second scrambler XORs second mask data corresponding to the address data and data after the conversion of the first scrambled data by the first converter and outputs obtained second scrambled data as the confidential data.
摘要翻译：数据处理装置包括地址总线，加扰单元和数据总线。地址总线输出要提供给存储装置的地址数据。加扰单元将写入数据加密到由地址数据识别的存储装置中的存储位置，以获得机密数据。数据总线输出机密数据。加扰单元包括第一加扰器，第一转换器和第二加扰器。第一加扰器将对应于地址数据的第一掩码数据和每个位的写入数据进行异或，并使其成为第一个加扰数据。第一转换器执行第一加扰数据的一对一替换转换。第二加扰器将对应于地址数据的第二掩码数据和由第一转换器转换第一加扰数据之后的数据进行异或，并将获得的第二加密数据作为机密数据输出。

6. 发明申请

US20100232601A1 ELLIPTIC CURVE ARITHMETIC PROCESSING UNIT AND ELLIPTIC CURVE ARITHMETIC PROCESSING PROGRAM AND METHOD 审中-公开
标题翻译：椭圆曲线算术处理单元和椭圆曲线算术处理程序和方法
公开(公告)号：US20100232601A1
公开(公告)日：2010-09-16
申请号：US12688033
申请日：2010-01-15
申请人： Kouichi ITOH , Dai Yamamoto , Tetsuya Izu , Masahiko Takenaka , Kazuyoshi Furukawa
发明人： Kouichi ITOH , Dai Yamamoto , Tetsuya Izu , Masahiko Takenaka , Kazuyoshi Furukawa
IPC分类号： H04L9/28
CPC分类号： G06F7/725 , G06F2207/7271
摘要： An apparatus for executing cryptographic calculation on the basis of an elliptic point on an elliptic curve includes: a memory for storing a first value including a plurality of digits; and a processor for executing a process including: obtaining a second value representing a point on the elliptic curve; calculating output values by using a predetermined equation, each digit of the first value, and the second value; determining whether at least one of the second value and the output values indicates a point of infinity; terminating the calculation when at least one of the second value and the output values indicates the point at infinity; and completing calculation when both the second value and the output values do not indicate the point at infinity, so as to obtain a result of the cryptographic calculation.
摘要翻译：一种用于基于椭圆曲线上的椭圆点执行加密计算的装置包括：存储器，用于存储包括多个数字的第一值; 以及用于执行处理的处理器，包括：获得表示所述椭圆曲线上的点的第二值; 通过使用预定方程，第一值的每个数字和第二值来计算输出值; 确定所述第二值和所述输出值中的至少一个是否指示无限点; 当所述第二值和所述输出值中的至少一个指示所述无限远点时终止所述计算; 并且当第二值和输出值都不表示无限远点时完成计算，以获得加密计算的结果。

7. 发明授权

US08352529B2 Modular multiplication calculation apparatus used for montgomery method 有权
标题翻译：用于montgomery方法的模块化乘法计算装置
公开(公告)号：US08352529B2
公开(公告)日：2013-01-08
申请号：US12218060
申请日：2008-07-11
申请人： Kazuyoshi Furukawa , Masahiko Takenaka
发明人： Kazuyoshi Furukawa , Masahiko Takenaka
IPC分类号： G06F7/38
CPC分类号： G06F7/728
摘要： REDC (A*B) is calculated for the values A and B by using a Montgomery's algorithm REDC. The part related to the A*B is performed by the three-input two-output product-sum calculation circuit. One digit ai of the value A, one digit bj of the value B and a carry value c1 are input to the product-sum calculation circuit, and ai*bj+c1 is calculated thereat. The higher-order digit of the r-adic two-digit of the calculation result is used as the carry value c1, and the lower digit is used for a later calculation. Further, one digit ni of a modulo N for the REDC, a predetermined value m and a carry value c2 are input into the product-sum calculation circuit, and n*ni+c2 is calculated thereat. The higher-order digit is used as the carry value c2, and the lower digit is used for a later calculation.
摘要翻译：通过使用蒙哥马利的算法REDC计算值A和B的REDC（A * B）。与A * B相关的部分由三输入双输出积和计算电路进行。值A的一位数ai，值B的一位数bj和进位值c1被输入到乘积和计算电路，并且在其计算ai * bj + c1。将计算结果的r-adic两位数的高阶数字用作进位值c1，将下位数用于后续计算。此外，对于REDC，模N的一位数ni，预定值m和进位值c2被输入到乘积和计算电路中，并且在那里计算n * ni + c2。高位数字用作进位值c2，下位数用于后续计算。

8. 发明授权

US08667302B2 Signature generating device and method, signature verifying device and method, and computer product 有权
标题翻译：签名生成装置和方法，签名验证装置和方法以及计算机产品
公开(公告)号：US08667302B2
公开(公告)日：2014-03-04
申请号：US12888553
申请日：2010-09-23
申请人： Takashi Yoshioka , Masahiko Takenaka , Fumitsugu Matsuo , Fumiaki Chiba
发明人： Takashi Yoshioka , Masahiko Takenaka , Fumitsugu Matsuo , Fumiaki Chiba
IPC分类号： G06F21/24
CPC分类号： G01N21/93 , G01N21/9501 , G01N2021/8861 , H04L9/3247 , H04N5/77
摘要： A signature generating device includes a receiving unit that receives a sequence of data; a summary data generating unit that generates summary data of the data upon reception of each of the data by the receiving unit; an obtaining unit that obtains, when the number of data included in a sequence of the generated summary data reaches a given number, the sequence of the summary data as a block; a setting unit that sets, as a signature subject, a current block constituted by the sequence of the summary data, and the summary data selected from at least one block contiguous to the current block; a digital signature generating unit that generates a digital signature concerning data summarized for the current block; and a sending unit that sends the generated digital signature, the signature subject associated with the digital signature, and the data summarized for the current block.
摘要翻译：签名产生装置包括：接收单元，其接收数据序列; 汇总数据生成单元，其通过接收单元接收到每个数据时生成数据的汇总数据; 获取单元，当所生成的汇总数据的序列中包括的数据的数量达到给定的数量时，获得作为块的汇总数据的序列; 设置单元，其将签名对象设置为由所述汇总数据的序列构成的当前块以及从与所述当前块相邻的至少一个块中选择的汇总数据; 数字签名生成单元，生成关于当前块的总结的数据的数字签名; 以及发送单元，其发送生成的数字签名，与数字签名相关联的签名主体以及针对当前块总结的数据。

9. 发明授权

US08638927B2 Cryptographic processing method, computer readable storage medium, and cryptographic processing device 有权
标题翻译：加密处理方法，计算机可读存储介质和密码处理装置
公开(公告)号：US08638927B2
公开(公告)日：2014-01-28
申请号：US12886051
申请日：2010-09-20
申请人： Masahiko Takenaka , Kouichi Itoh
发明人： Masahiko Takenaka , Kouichi Itoh
IPC分类号： H04K1/00
CPC分类号： G06F7/723 , G06F2207/7242 , H04L9/003 , H04L9/302 , H04L2209/127
摘要： 401 stores, in 302, key d′ obtained by subtracting random number 2r held in 201 from key d held in 105. When an operation starts, the values “−C” and “−C2” are calculated respectively, and the resultant values are stored in a multiplication table memory 205 together with value “C”. In a first operation cycle, 107 selects and outputs an intermediate value 108 held in an in-operation data register 103, and thereby makes a modular-multiplication operation circuit 104 perform squaring. In the second operation cycle, 107 selects and outputs one of three values held in 205 in accordance with the combination of key bit value d′i and random number bit value ri, and thereby makes the modular-multiplication operation circuit 104 perform multiplication. Thereby, a cryptographic processing device that requires a short operation time period, small circuit scale, and has sufficient security can be realized.
摘要翻译： 401在302中存储通过从保持在105中的密钥d减去在201中保留的随机数2r获得的密钥d'。当操作开始时，分别计算值“-C”和“-C2”，并且得到的值为与值“C”一起存储在乘法表存储器205中。在第一操作周期中，107选择并输出保持在工作数据寄存器103中的中间值108，从而使得乘法运算电路104进行平方。在第二操作周期中，107根据密钥位值d i和随机数位值ri的组合来选择并输出保持在205中的三个值之一，从而使乘法运算电路104进行乘法运算。因此，可以实现需要短操作时间段，小电路规模并且具有足够安全性的密码处理装置。

10. 发明授权

US08369516B2 Encryption apparatus having common key encryption function and embedded apparatus 有权
标题翻译：具有公共密钥加密功能的加密装置和嵌入式装置
公开(公告)号：US08369516B2
公开(公告)日：2013-02-05
申请号：US12889096
申请日：2010-09-23
申请人： Kouichi Itoh , Souichi Okada , Masahiko Takenaka
发明人： Kouichi Itoh , Souichi Okada , Masahiko Takenaka
IPC分类号： G06F21/00
CPC分类号： H04L9/0631 , H04L9/003 , H04L2209/046 , H04L2209/08 , H04L2209/122
摘要： A common key block encryption apparatus for performing a nonlinear transformation with a multiplication executed in a binary field or a composite field includes a computing unit to execute a computation other than the nonlinear transformation with fixed value masked input data obtained by XORing input data with a fixed mask value, an XOR operation circuit to transform all input data into fixed value masked input data by XORing the input data with a fixed mask value and to transform the data into random value masked input data by XORing the input data with a random mask value in the multiplication, a multiplier to execute a multiplication based on the random value masked input data output from the XOR operation circuit, and a random value mask-to-fixed mask value transformation circuit to again transform the random value masked output data into fixed value masked output data and to output the data.
摘要翻译：用于通过在二进制字段或复合字段中执行的乘法执行非线性变换的公共密钥块加密装置包括：计算单元，用于执行非线性变换以外的计算，该固定值掩码输入数据通过将具有固定值的输入数据进行异或掩模值，XOR运算电路，通过用固定的掩码值对输入数据进行异或，将所有输入数据变换为固定值掩码输入数据，并通过将输入数据以随机掩码值进行异或来将数据变换为随机值屏蔽输入数据乘法，乘法器，用于根据从异或运算电路输出的随机值屏蔽输入数据执行乘法，以及随机值掩码到固定掩码值变换电路，以将随机值屏蔽输出数据再次转换为固定值掩码输出数据并输出数据。

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