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1. 发明授权

US5257230A Memory device including redundancy cells with programmable fuel elements and process of manufacturing the same 失效
标题翻译：存储器件包括具有可编程燃料元件的冗余单元及其制造过程
公开(公告)号：US5257230A
公开(公告)日：1993-10-26
申请号：US565820
申请日：1990-08-13
申请人： Kazuhiko Nobori , Taira Iwase , Masamichi Asano , Makoto Takizawa , Shigefumi Ishiguro , Kazuo Yonehara , Satoshi Nikawa , Koji Saito
发明人： Kazuhiko Nobori , Taira Iwase , Masamichi Asano , Makoto Takizawa , Shigefumi Ishiguro , Kazuo Yonehara , Satoshi Nikawa , Koji Saito
IPC分类号： H01L21/82 , G11C29/00 , H01L21/8246 , H01L23/525 , H01L27/10 , G11C17/16
CPC分类号： G11C29/785 , H01L23/5256 , H01L27/1126 , H01L2924/0002
摘要： There is disclosed an improved semiconductor memory device having a regular memory cell array and a spare memory cell array. Each spare memory cell constituting the spare memory cell array includes a first transistor selected by a read word line, whose drain is connected to a spare bit line and source is connected via a fuse to a power supply, and a second transistor connected between the interconnection between the first transistor and fuse and a ground. The fuse is selectively blown by flowing a blowing current through the fuse by selecting the second transistor through a write line to thereby disconnect a discharge current path of the spare bit line. The threshold voltage of the second transistor of the spare memory cell which is made conductive upon selection by the write line when the blowing current flows through the fuse is higher than a potential difference between a potential generated at the write line connected with another spare memory cell and a ground potential. Such a high threshold voltage is obtained by including in manufacture of the memory cell the steps of implanting impurity ions of a first conductivity type to the channel area of a region on the surface of a semiconductor substrate where transistors including the second transistor of a second conductivity type different from the first conductivity type are formed; and implanting impurity ions of the one conductivity type to the channel area of the second transistor and to the channel area of transistors of a conductivity type different from the second transistor; whereby the impurity ions are implanted twice to the channel area of the second transistor.

2. 发明授权

US5208780A Structure of electrically programmable read-only memory cells and redundancy signature therefor 失效
标题翻译：电可编程只读存储单元的结构和冗余签名
公开(公告)号：US5208780A
公开(公告)日：1993-05-04
申请号：US731467
申请日：1991-07-17
申请人： Taira Iwase , Makoto Takizawa , Shigefumi Ishiguro , Kazuhiko Nobori
发明人： Taira Iwase , Makoto Takizawa , Shigefumi Ishiguro , Kazuhiko Nobori
IPC分类号： G11C17/16 , G11C29/00
CPC分类号： G11C29/835 , G11C17/16
摘要： In an electrically programmable ROM, each cell 13 includes a series-connected element composed of a combination writing and reading transistor 17 and a fuse 15. One end of this series-connected element is connected to a corresponding bit line 19, and the other end thereof is grounded. A gate of the transistor 17 of the series-connected element is connected to a corresponding word line 23. Each bit line 19 is connected to a high-voltage applying pad 21 via an element such as diode or transistor provided with electrically connecting/isolating functions. When a data is written in the memory cell 13, the high-voltage applying pad 21 is electrically connected to the bit line 19. Under these conditions, if a high voltage is applied to the high-voltage applying pad 21, the transistor 17 performs snap-back action (i.e. secondary breakdown) to blow out the fuse 15. When the data is read, the high-voltage applying pad 21 is isolated from the bit line 19 without exerting influence upon the read out operation. In addition, in the above-mentioned electrically programmable ROM, a circuit for electrically blowing out the fuse by utilizing transistor's snap-back action is used as a redundancy signature indicative of whether the redundancy circuit is used or unused.
摘要翻译：在电可编程ROM中，每个单元13包括由写入和读取晶体管17和熔丝15组成的串联元件。该串联元件的一端连接到对应的位线19，而另一端它接地。串联元件的晶体管17的栅极连接到相应的字线23.每个位线19经由诸如具有电连接/隔离功能的二极管或晶体管的元件连接到高压施加焊盘21 。当数据被写入存储单元13时，高压施加焊盘21与位线19电连接。在这些条件下，如果向高压施加焊盘21施加高电压，则晶体管17执行回扫动作（即二次击穿）以吹出保险丝15.当读取数据时，高压施加垫21与位线19隔离，而不会对读出操作产生影响。此外，在上述电气可编程ROM中，使用用于通过利用晶体管的快速恢复动作来电熔熔丝的电路作为指示冗余电路是否被使用或未被使用的冗余标记。

3. 发明授权

US5124948A Mask ROM with spare memory cells 失效
标题翻译：掩膜ROM与备用存储单元
公开(公告)号：US5124948A
公开(公告)日：1992-06-23
申请号：US751574
申请日：1991-08-22
申请人： Makoto Takizawa , Taira Iwase , Masamichi Asano , Yasunori Arime
发明人： Makoto Takizawa , Taira Iwase , Masamichi Asano , Yasunori Arime
IPC分类号： G11C29/00
CPC分类号： G11C29/822
摘要： A main memory cell array is divided into a plurality of blocks, and a spare memory cell group is arranged apart from the main memory cell array. The spare memory cell group uses bit lines or word lines different from those of the main memory cell array and includes spare memory cells which are different in structure from the memory cells of the main memory cell array. The number of the memory cells of the spare memory cell group is the same as that of the main memory cells of one row or column in each block of the main memory cell array, and data can be programmed into the spare memory cells after the completion of the manufacturing process. The operation of programming data into the spare memory cells of the spare memory cell array is effected by use of a write-in address buffer and a write-in decoder. When a row or column including a defective memory cell is designated in the main memory cell array, the row or column of the spare memory cells in the spare memory cell group is activated.
摘要翻译：主存储单元阵列被分成多个块，并且备用存储单元组被布置成与主存储单元阵列分开。备用存储单元组使用与主存储单元阵列不同的位线或字线，并且包括与主存储单元阵列的存储单元结构不同的备用存储单元。备用存储单元组的存储单元的数量与主存储单元阵列的每个块中的一个行或列的主存储单元的数量相同，并且可以在完成后将数据编程到备用存储单元中的制造过程。通过使用写入地址缓冲器和写入解码器来实现将数据编程到备用存储单元阵列的备用存储单元中的操作。当在主存储单元阵列中指定包括有缺陷存储单元的行或列时，备用存储单元组中的备用存储单元的行或列被激活。

4. 发明授权

US4970686A Semiconductor memory cells and semiconductor memory device employing the semiconductor memory cells 失效
标题翻译：采用半导体存储单元的半导体存储单元和半导体存储器件
公开(公告)号：US4970686A
公开(公告)日：1990-11-13
申请号：US396246
申请日：1989-08-21
申请人： Yasuo Naruke , Thoru Mochizuki , Taira Iwase , Masamichi Asano
发明人： Yasuo Naruke , Thoru Mochizuki , Taira Iwase , Masamichi Asano
IPC分类号： G11C17/00 , G11C17/12 , G11C17/14 , G11C29/00 , G11C29/04
CPC分类号： G11C29/785 , G11C17/12
摘要： A spare memory cell comprises a read FET (Field Effect Transistor), a fusing FET and a current fuse. The FETs are connected in series between a read data line and a low voltage source. The fuse is inserted between a series node of the FETs and a write data line. The fuse is molten when data is written to the spare memory cell. By applying a power source voltage to a control electrode of the fusing FET and by applying a voltage that is higher than the power source voltage to the write data line, the fusing FET is set to its secondary breakdown state. Under this state, a large current flows through the fusing FET to cut off the fuse, thus writing data to the spare memory cell.

5. 发明授权

US6034910A Semiconductor memory device to which serial access is made and a method for accessing the same 有权
标题翻译：进行串行访问的半导体存储器件及其访问方法
公开(公告)号：US6034910A
公开(公告)日：2000-03-07
申请号：US204776
申请日：1998-12-03
申请人： Taira Iwase
发明人： Taira Iwase
IPC分类号： G11C17/18 , G11C7/10 , G11C8/04 , G11C7/00
CPC分类号： G11C7/1036 , G11C7/1006 , G11C7/1018 , G11C7/1039
摘要： A memory cell array is divided into a plurality of blocks and sense amplifiers and shift registers are provided for the respective blocks. After a plurality of data sets are read out in the first random access cycle and transferred to each of the shift registers, column switching is made and a plurality of next data sets are read out. Then, the pipeline processing for the data items is effected to serially read out data in the serial access cycle.
摘要翻译：存储单元阵列被分成多个块，读出放大器和各个块提供移位寄存器。在第一随机存取周期中读出多个数据组并传送到每个移位寄存器之后，进行列切换，并读出多个下一个数据组。然后，进行用于数据项的流水线处理以串行读取串行访问周期中的数据。

6. 发明授权

US5392233A Read only memory capable of realizing high-speed read operation 失效
标题翻译：只读存储器，能够实现高速读取操作
公开(公告)号：US5392233A
公开(公告)日：1995-02-21
申请号：US991642
申请日：1992-12-16
申请人： Taira Iwase
发明人： Taira Iwase
IPC分类号： G11C17/12 , H01L21/8246 , H01L27/112 , G11C17/00 , G11C11/34
CPC分类号： H01L27/112 , G11C17/126
摘要： A mask read only memory (ROM) has a small chip size and realizes high-speed operation and a large capacity by reducing a wiring capacity of a main bit line and a virtual ground line. Between the main bit line and the virtual ground line are three bit lines, and between the main bit line and the virtual ground line are formed two columns of memory cell transistor columns in the direction of the word line, Furthermore, the main bit line and the virtual ground line do not have zig-zag wiring, and can be configured so that the lines are in parallel straight lines so that the connections between the bit lines and the main bit lines, and between the bit lines and the virtual ground lines can be suitably made or broken by a drive current supplied via a selector line and using transistors as gates, to therefore enable the selection of a required memory cell transistor column by on-off control,
摘要翻译：掩模只读存储器（ROM）具有小的芯片尺寸，通过减少主位线和虚拟接地线的布线容量实现高速操作和大容量。在主位线和虚拟接地线之间是三位线，并且在主位线和虚拟接地线之间在字线的方向上形成两列存储单元晶体管列，此外，主位线和虚拟接地线不具有锯齿形布线，并且可以被配置为使得线路是平行的直线，使得位线和主位线之间以及位线和虚拟接地线之间的连接可以由通过选择线提供的驱动电流适当地制造或断开，并且使用晶体管作为栅极，因此能够通过开关控制来选择所需的存储单元晶体管列，

7. 发明授权

US06864719B2 Semiconductor device protecting built-in transistor from the voltage applied at test mode 失效
标题翻译：半导体器件保护内置晶体管与测试模式下施加的电压
公开(公告)号：US06864719B2
公开(公告)日：2005-03-08
申请号：US10401585
申请日：2003-03-31
申请人： Taira Iwase
发明人： Taira Iwase
IPC分类号： G01R31/28 , G01R31/317 , H01L21/822 , H01L27/04 , H03K19/0175
CPC分类号： G01R31/2884 , G01R31/31701 , G01R31/3172
摘要： A semiconductor device comprises a high-voltage detector for generating a test mode signal and a detection signal when a test mode setting signal is inputted from an input terminal for inputting, as a first input signal, any one of a normal signal and the test mode setting signal having a higher voltage than the normal signal, an input circuit for generating a normal mode signal in accordance with the normal signal, and a protection circuit for reducing an electric field between an input side and a low-voltage power supply side of the input circuit in accordance with the detection signal, the electric field being generated by inputting the test mode setting signal thereto.
摘要翻译：半导体器件包括用于产生测试模式信号的高电压检测器和当从用于输入正常信号和测试模式中的任何一个作为第一输入信号的输入端子输入测试模式设置信号时的检测信号具有比正常信号高的电压的设定信号，用于根据正常信号产生正常模式信号的输入电路和用于减小所述正常信号的输入侧和低电压电源侧之间的电场的保护电路输入电路根据检测信号，通过向其输入测试模式设定信号而产生电场。

8. 发明授权

US5403765A Method of manufacturing double-layer gate programmable ROM 失效
标题翻译：制造双层门可编程ROM的方法
公开(公告)号：US5403765A
公开(公告)日：1995-04-04
申请号：US121519
申请日：1993-09-16
申请人： Taira Iwase
发明人： Taira Iwase
IPC分类号： G11C17/12 , H01L21/8246 , H01L21/8247 , H01L27/112 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/265
CPC分类号： H01L27/112
摘要： A method of manufacturing a double-layer gate programmable ROM is disclosed including the steps of: forming a plurality of first gate layers at predetermined intervals on a semiconductor substrate, source and drain regions being formed on the surface of the semiconductor substrate and under the first gate layers, respectively; forming a plurality of second gate layers between the first gate layers, channel regions being formed on the surface of the semiconductor substrate and under the second gate layers, respectively; and selectively implanting ions into the channel regions to program data. In particular, the second gates are formed between the first gate layers so as to provide partial vertically overlapped portions at which one end of each of the second gate layers is overlapped partially with the other end of each of the first gate layers, respectively, and the ion implantation into the channel regions is effected under such a condition that ions can penetrate the first and second layers, but cannot penetrate the overlapped portions of both the first and second layers. Transistors are first formed having a first E-type threshold voltage. Selective ion implantation lowers the threshold voltage of certain of the transistors to program the data into the ROM.
摘要翻译：公开了一种制造双层栅可编程ROM的方法，包括以下步骤：在半导体衬底上以预定的间隔形成多个第一栅极层，在半导体衬底的表面上形成源极和漏极区，栅极层; 在所述第一栅极层之间形成多个第二栅极层，沟道区分别形成在所述半导体衬底的表面上和所述第二栅极层下方; 并且选择性地将离子注入到通道区域中以对数据进行编程。特别地，第二栅极形成在第一栅极层之间，以便分别提供部分垂直重叠的部分，其中每个第二栅极层的一端分别与每个第一栅极层的另一端重叠，在离子可以穿透第一层和第二层但不能穿透第一层和第二层的重叠部分的条件下进行到沟道区的离子注入。首先形成具有第一E型阈值电压的晶体管。选择性离子注入降低了某些晶体管的阈值电压以将数据编程到ROM中。

9. 发明授权

US5172337A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5172337A
公开(公告)日：1992-12-15
申请号：US778064
申请日：1991-12-06
申请人： Taira Iwase , Yasuo Naruke
发明人： Taira Iwase , Yasuo Naruke
IPC分类号： G11C17/14 , G11C17/16 , H01L21/82 , H01L27/10
CPC分类号： G11C17/16
摘要： A semiconductor memory device of the present invention is a semiconductor memory device formed on a semiconductor layer (30) of a first conductivity type and having a plurality of fuse melting type non-volatile memory cells (1) disposed generally in a matrix form, wherein the memory cell (1) has a read transistor (3), a current-melting fuse (7), and a fuse blow transistor (5), one end of the read transistor (3) is connected to a read data line (13), the other end thereof is connected via the current-melting fuse (7) to a write data line (17), an interconnection (C.sub.1) between the read transistor (3) and the fuse (7) is connected via the fuse blow transistor (5) to ground by a ground wiring (15), the write data lines (17) and the ground wirings (15) of the memory cells (1) disposed in a row direction are connected in common, and a noise absorbing element (21) is connected between the write data line (17) and the ground wiring (15), the noise absorbing element (21) suppressing a potential difference between the write data line (17) and the ground wiring (15) from becoming large.
摘要翻译： PCT No.PCT / JP91 / 00459 Sec。 371 1991年12月6日第 102（e）1991年12月6日授权PCT 1991年4月6日PCT。本发明的半导体存储器件是形成在第一导电类型的半导体层（30）上并具有多个保险丝熔融型非易失性存储单元（1），其通常以矩阵形式布置，其中所述存储单元（1）具有读取晶体管（3），电流熔断熔丝（7）和熔丝熔断晶体管（5）读取晶体管（3）的一端连接到读取数据线（13），其另一端通过电流熔断熔丝（7）连接到写入数据线（17），互连（C1）读取晶体管（3）和熔丝（7）经由熔丝熔断晶体管（5）通过接地布线（15），存储单元的写入数据线（17）和接地布线（15）连接到地在行方向上配置的（1）共同连接，并且在写入数据线（17）和接地布线（15）之间连接有噪声吸收元件（21），噪声抑制写入数据线（17）和接地布线（15）之间的电位差的吸收元件（21）变大。

10. 发明授权

US4649412A Read only semiconductor memory device with polysilicon drain extensions 失效
标题翻译：只读半导体存储器件，具有多晶硅漏极延伸
公开(公告)号：US4649412A
公开(公告)日：1987-03-10
申请号：US674999
申请日：1984-11-27
申请人： Taira Iwase , Shoji Ariizumi , Fujio Masuoka
发明人： Taira Iwase , Shoji Ariizumi , Fujio Masuoka
IPC分类号： H01L29/78 , H01L21/8246 , H01L23/522 , H01L27/10 , H01L27/112 , G11C11/40 , H01L27/04
CPC分类号： H01L27/1126 , H01L23/5226 , H01L27/112 , H01L2924/0002 , Y10S148/082 , Y10S148/109
摘要： A semiconductor memory device is formed of a polycrystalline silicon electrode terminal layer, which is formed on a MOS transistor except over the gate region and is connected to the drain region of the MOS transistor, and metal wire layer, which is formed on the MOS transistor except over the gate region and is connected to the electrode terminal layer to transmit output signals. Data is written into the semiconductor memory device by ion implantation of the gate of the MOS transistor after the metal wire layer is formed.
摘要翻译：半导体存储器件由多晶硅电极端子层形成，该多晶硅电极端子层形成在栅极区以外的MOS晶体管上并与MOS晶体管的漏极区连接，金属线层形成在MOS晶体管上除了在栅极区域之外，并且连接到电极端子层以传输输出信号。在形成金属线层之后，通过离子注入MOS晶体管的栅极将数据写入半导体存储器件。

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