专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060062341A1 Fast-lock clock-data recovery system 审中-公开
标题翻译：快速锁定时钟数据恢复系统
公开(公告)号：US20060062341A1
公开(公告)日：2006-03-23
申请号：US11016513
申请日：2004-12-17
申请人： John Edmondson , John Eble , Ramin Farjad-rad , Shadi Barakat
发明人： John Edmondson , John Eble , Ramin Farjad-rad , Shadi Barakat
IPC分类号： H03D3/24
CPC分类号： H03L7/0814 , H03L7/07 , H03L7/091 , H03L7/107 , H04L7/0025 , H04L7/0337
摘要： A fast-locking clock-data recovery (CDR) system. The CDR system slews the phase of a sampling clock signal at a first slew rate in response to detecting an out-of-alignment condition between a first sampling clock signal and a data signal. Then, after exiting the out-of-alignment condition, the CDR system slews the phase of the sampling clock signal at a second, slower slew rate.
摘要翻译：快速锁定时钟数据恢复（CDR）系统。响应于检测到第一采样时钟信号和数据信号之间的不对齐状态，CDR系统以第一转换速率旋转采样时钟信号的相位。然后，在退出不对准状态之后，CDR系统以第二个较慢的转换速率旋转采样时钟信号的相位。

2. 发明授权

US08245073B2 Method and apparatus synchronizing integrated circuit clocks 有权
标题翻译：方法和装置同步集成电路时钟
公开(公告)号：US08245073B2
公开(公告)日：2012-08-14
申请号：US12509409
申请日：2009-07-24
申请人： Aaron Nygren , Ming-Ju Edward Lee , Shadi Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger , Michael Litt
发明人： Aaron Nygren , Ming-Ju Edward Lee , Shadi Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger , Michael Litt
IPC分类号： G06F1/12
CPC分类号： G11C7/1045
摘要： Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.
摘要翻译：本文描述的实施例包括用于在计算机系统中的耦合集成电路（IC）之间同步时钟的方法和系统。根据实施例，在第一IC上提供专用定时引脚。第一IC配置第二IC以改变引脚分配，使得第二IC解释由第一IC在定时引脚上发送的信号，并且在重新分配的引脚上接收作为发送返回信号的请求的信号。在定时引脚上接收到返回信号。返回信号用于确定是否应由第一个IC调整定时。在一个实施例中，时钟和数据恢复（CDR）电路将发送的信号与所接收的信号进行比较，以进行确定。在一个实施例中，第一IC是基于处理器的设备，第二IC是由第一设备控制的存储设备。

3. 发明授权

US09223541B2 Method and apparatus to eliminate frequency holes in a memory I/O system 有权
标题翻译：消除存储器I / O系统中的频率孔的方法和装置
公开(公告)号：US09223541B2
公开(公告)日：2015-12-29
申请号：US13682487
申请日：2012-11-20
申请人： Shadi Barakat
发明人： Shadi Barakat
IPC分类号： G06F1/10 , G06F5/06
CPC分类号： G06F5/065 , G06F1/10 , G06F2205/067
摘要： Various methods and apparatus for managing signals between a processor and a memory device are disclosed. In one aspect, a method of managing signals between a processor and a memory device wherein the processor and the memory device are operatively coupled by a data signal path and a clock signal path is provided. The method includes setting the skew between the data signal path and the clock signal path away from a spectral peak of a phase jitter transfer function.
摘要翻译：公开了用于在处理器和存储器件之间管理信号的各种方法和装置。一方面，提供一种管理处理器和存储器件之间的信号的方法，其中处理器和存储器件通过数据信号路径和时钟信号路径可操作地耦合。该方法包括将数据信号路径和时钟信号路径之间的偏差设置为远离相位抖动传递函数的频谱峰值。

4. 发明申请

US20140143585A1 METHOD AND APPARATUS TO ELIMINATE FREQUENCY HOLES IN A MEMORY I/O SYSTEM 有权
标题翻译：在存储器I / O系统中消除频率的方法和装置
公开(公告)号：US20140143585A1
公开(公告)日：2014-05-22
申请号：US13682487
申请日：2012-11-20
申请人： Shadi Barakat
发明人： Shadi Barakat
IPC分类号： G06F1/10
CPC分类号： G06F5/065 , G06F1/10 , G06F2205/067
摘要： Various methods and apparatus for managing signals between a processor and a memory device are disclosed. In one aspect, a method of managing signals between a processor and a memory device wherein the processor and the memory device are operatively coupled by a data signal path and a clock signal path is provided. The method includes setting the skew between the data signal path and the clock signal path away from a spectral peak of a phase jitter transfer function.
摘要翻译：公开了用于在处理器和存储器件之间管理信号的各种方法和装置。一方面，提供一种管理处理器和存储器件之间的信号的方法，其中处理器和存储器件通过数据信号路径和时钟信号路径可操作地耦合。该方法包括将数据信号路径和时钟信号路径之间的偏差设置为远离相位抖动传递函数的频谱峰值。

5. 发明授权

US08443225B2 Method and apparatus synchronizing integrated circuit clocks 有权
标题翻译：方法和装置同步集成电路时钟
公开(公告)号：US08443225B2
公开(公告)日：2013-05-14
申请号：US13584560
申请日：2012-08-13
申请人： Aaron Nygren , Ming-Ju Edward Lee , Shadi Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger , Michael Litt
发明人： Aaron Nygren , Ming-Ju Edward Lee , Shadi Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger , Michael Litt
IPC分类号： G06F1/12
CPC分类号： G11C7/1045
摘要： Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.
摘要翻译：本文描述的实施例包括用于在计算机系统中的耦合集成电路（IC）之间同步时钟的方法和系统。根据实施例，在第一IC上提供专用定时引脚。第一IC配置第二IC以改变引脚分配，使得第二IC解释由第一IC在定时引脚上发送的信号，并且在重新分配的引脚上接收作为发送返回信号的请求的信号。在定时引脚上接收到返回信号。返回信号用于确定是否应由第一个IC调整定时。在一个实施例中，时钟和数据恢复（CDR）电路将发送的信号与所接收的信号进行比较，以进行确定。在一个实施例中，第一IC是基于处理器的设备，第二IC是由第一设备控制的存储设备。

6. 发明申请

US20120303995A1 METHOD AND APPARATUS SYNCHRONIZING INTEGRATED CIRCUIT CLOCKS 有权
标题翻译：方法和装置同步集成电路时钟
公开(公告)号：US20120303995A1
公开(公告)日：2012-11-29
申请号：US13584560
申请日：2012-08-13
申请人： Aaron Nygren , Ming-Ju Edward Lee , Shadi Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger , Michael Litt
发明人： Aaron Nygren , Ming-Ju Edward Lee , Shadi Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger , Michael Litt
IPC分类号： G06F1/12 , G06F1/04
CPC分类号： G11C7/1045
摘要： Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.
摘要翻译：本文描述的实施例包括用于在计算机系统中的耦合集成电路（IC）之间同步时钟的方法和系统。根据实施例，在第一IC上提供专用定时引脚。第一IC配置第二IC以改变引脚分配，使得第二IC解释由第一IC在定时引脚上发送的信号，并且在重新分配的引脚上接收作为发送返回信号的请求的信号。在定时引脚上接收到返回信号。返回信号用于确定是否应由第一个IC调整定时。在一个实施例中，时钟和数据恢复（CDR）电路将发送的信号与所接收的信号进行比较，以进行确定。在一个实施例中，第一IC是基于处理器的设备，第二IC是由第一设备控制的存储设备。

7. 发明申请

US20120017118A1 METHOD AND APPARATUS FOR TESTING AN INTEGRATED CIRCUIT INCLUDING AN I/O INTERFACE 审中-公开
标题翻译：用于测试包含I / O接口的集成电路的方法和装置
公开(公告)号：US20120017118A1
公开(公告)日：2012-01-19
申请号：US12838860
申请日：2010-07-19
申请人： Shadi Barakat , Petre Popescu , David Block
发明人： Shadi Barakat , Petre Popescu , David Block
IPC分类号： G06F11/263
CPC分类号： G06F11/221
摘要： Methods and apparatus provide for testing an integrated circuit including an input/output (I/O) interface. The method and apparatus place the I/O interface in a test mode by test enabling logic. During the test mode, the method and apparatus also provide, by a clock generator in the I/O interface, an internal phase-aligned receiver clock signal to a plurality of transceivers in the I/O interface. The clock generator is a transmitter portion of one of the plurality of transceivers in the I/O interface. The method and apparatus then monitor for errors in loopback data from the plurality of transceivers in the I/O interface by an automatic test equipment (ATE). The phase of the internal phase-aligned receiver clock signal is aligned with the loopback data of the plurality of transceivers, and the frequency of the internal phase-aligned receiver clock signal may be above about 200 MHz.
摘要翻译：方法和装置提供测试包括输入/输出（I / O）接口的集成电路。该方法和设备通过测试启用逻辑将I / O接口置于测试模式。在测试模式期间，该方法和装置还通过I / O接口中的时钟发生器将内部相位对准接收机时钟信号提供给I / O接口中的多个收发器。时钟发生器是I / O接口中的多个收发器之一的发射机部分。然后，该方法和装置通过自动测试设备（ATE）监视来自I / O接口中的多个收发器的环回数据中的错误。内部相位对准的接收器时钟信号的相位与多个收发器的回送数据对准，并且内部相位对准的接收机时钟信号的频率可以高于约200MHz。

8. 发明申请

US20110019787A1 Method and Apparatus Synchronizing Integrated Circuit Clocks 有权
标题翻译：同步集成电路时钟的方法和装置
公开(公告)号：US20110019787A1
公开(公告)日：2011-01-27
申请号：US12509409
申请日：2009-07-24
申请人： Aaron Nygren , Ming-Ju Edward Lee , Shadi Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger , Michael Litt
发明人： Aaron Nygren , Ming-Ju Edward Lee , Shadi Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger , Michael Litt
IPC分类号： H04L7/00 , H03K19/096
CPC分类号： G11C7/1045
摘要： Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.
摘要翻译：本文描述的实施例包括用于在计算机系统中的耦合集成电路（IC）之间同步时钟的方法和系统。根据实施例，在第一IC上提供专用定时引脚。第一IC配置第二IC以改变引脚分配，使得第二IC解释由第一IC在定时引脚上发送的信号，并且在重新分配的引脚上接收作为发送返回信号的请求的信号。在定时引脚上接收到返回信号。返回信号用于确定是否应由第一个IC调整定时。在一个实施例中，时钟和数据恢复（CDR）电路将发送的信号与所接收的信号进行比较，以便进行确定。在一个实施例中，第一IC是基于处理器的设备，第二IC是由第一设备控制的存储设备。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式