专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 外观设计

USD631184S1 Lens 有权
标题翻译：镜片
公开(公告)号：USD631184S1
公开(公告)日：2011-01-18
申请号：US29341132
申请日：2009-07-31
申请人： Jia-Chi Feng , Cheng-Hung Yu
设计人： Jia-Chi Feng , Cheng-Hung Yu

2. 外观设计

USD619154S1 Lens 有权
标题翻译：镜片
公开(公告)号：USD619154S1
公开(公告)日：2010-07-06
申请号：US29311907
申请日：2009-07-29
申请人： Jia-Chi Feng , Cheng-Hung Yu
设计人： Jia-Chi Feng , Cheng-Hung Yu

3. 发明授权

US08765333B2 Color filter array having hybrid color filters and manufacturing method thereof 有权
标题翻译：具有混合滤色器的滤色器阵列及其制造方法
公开(公告)号：US08765333B2
公开(公告)日：2014-07-01
申请号：US13561103
申请日：2012-07-30
申请人： Cheng-Hung Yu
发明人： Cheng-Hung Yu
IPC分类号： G02B5/20 , G03F7/20
CPC分类号： G02B5/201 , G03F7/0007
摘要： A method for manufacturing a color filter array having hybrid color filters includes providing a high-grade photoresist and a low-grade photoresist, forming a plurality of first color filters on a substrate, and forming a plurality of second color filters and a plurality of third color filters on the substrate. The first color filters include the high-grade photoresist, and the second color filters and the third color filters include the low-grade photoresist. The high-grade photoresist of the first color filters includes a first amount of large size pigments in one unit area and the low-grade photoresists of the second color filters and the third color filters include a second amount of large size pigments in one unit area. A ratio of the second amount to the first amount is equal to or larger than 1.
摘要翻译：一种制造具有混合滤色器的滤色器阵列的方法，包括提供高级光致抗蚀剂和低等级光致抗蚀剂，在衬底上形成多个第一滤色器，以及形成多个第二滤色器和多个第三滤色器基底上的滤色器。第一滤色器包括高级光致抗蚀剂，第二滤色器和第三滤色器包括低等级光致抗蚀剂。第一滤色器的高级光致抗蚀剂包括在一个单位面积中的第一量的大尺寸颜料和第二滤色器的低等级光致抗蚀剂和第三滤色器在一个单位面积中包括第二量的大尺寸颜料。第二量与第一量的比例等于或大于1。

4. 发明申请

US20110253435A1 MULTILAYER THREE-DIMENSIONAL CIRCUIT STRUCTURE 审中-公开
标题翻译：多层三维电路结构
公开(公告)号：US20110253435A1
公开(公告)日：2011-10-20
申请号：US13166133
申请日：2011-06-22
申请人： Han-Pei Huang , Cheng-Hung Yu
发明人： Han-Pei Huang , Cheng-Hung Yu
IPC分类号： H05K1/03 , H05K1/11
CPC分类号： H05K3/4644 , B33Y10/00 , B33Y80/00 , H05K1/0284 , H05K3/046 , H05K3/06 , H05K3/185 , H05K3/205 , H05K3/386 , H05K2201/0236 , H05K2201/09118 , H05K2203/0108 , H05K2203/013 , H05K2203/107 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49165
摘要： A multilayer three-dimensional circuit structure and a manufacturing method thereof are provided in the present invention. The manufacturing method includes following steps. First, a three-dimensional insulating structure is provided. A first three-dimensional circuit structure is then formed on a surface of the three-dimensional insulating structure. Next, an insulating layer covering the first three-dimensional circuit structure is formed. Thereafter, a second three-dimensional circuit structure is formed on the insulating layer. Subsequently, at least a conductive via penetrating the insulating layer is formed for electrically connecting the second three-dimensional circuit structure and the first three-dimensional circuit structure.
摘要翻译：本发明提供了一种多层三维电路结构及其制造方法。制造方法包括以下步骤。首先，提供三维绝缘结构。然后在三维绝缘结构的表面上形成第一三维电路结构。接下来，形成覆盖第一三维电路结构的绝缘层。此后，在绝缘层上形成第二三维电路结构。随后，至少形成了穿过绝缘层的导电通孔，用于电连接第二三维电路结构和第一三维电路结构。

5. 发明申请

US20110212567A1 METHOD OF FABRICATING IMAGE SENSOR AND REWORKING METHOD THEREOF 有权
标题翻译：制作图像传感器的方法及其制作方法
公开(公告)号：US20110212567A1
公开(公告)日：2011-09-01
申请号：US12714093
申请日：2010-02-26
申请人： Hsin-Ting TSAI , Cheng-Hung Yu , Chin-Kuang Liu , Kun-Yen Hsu
发明人： Hsin-Ting TSAI , Cheng-Hung Yu , Chin-Kuang Liu , Kun-Yen Hsu
IPC分类号： H01L31/0232 , H01L31/18 , H01L27/14
CPC分类号： H01L27/14687 , H01L27/14636 , H01L27/14685
摘要： A method of fabricating an image sensor device is provided. First, a substrate comprising a pixel array region and a pad region is provided. A patterned metal layer and a first planarization layer having an opening exposing the patterned metal layer in the pad region are sequentially formed on the substrate. A color filter array is formed on the first planarization layer in the pixel array region. A second planarization layer is formed to cover the color filter array and filled into the opening. A plurality of microlens is formed above the color filter array on the second planarization layer. A capping layer is conformally formed on the microlens and the second planarization layer. An etching step is performed to remove the capping layer and the second planarization layer in the opening so as to expose the patterned metal layer in the pad region.
摘要翻译：提供一种制造图像传感器装置的方法。首先，提供包括像素阵列区域和衬垫区域的衬底。图案化金属层和具有露出焊盘区域中的图案化金属层的开口的第一平坦化层依次形成在基板上。在像素阵列区域中的第一平坦化层上形成滤色器阵列。形成第二平坦化层以覆盖滤色器阵列并填充到开口中。在第二平坦化层上的滤色器阵列上方形成多个微透镜。覆盖层保形地形成在微透镜和第二平坦化层上。执行蚀刻步骤以去除开口中的覆盖层和第二平坦化层，以暴露焊盘区域中的图案化金属层。

6. 发明授权

US08003983B2 Wafer for manufacturing image sensors, test key layout for defects inspection, and methods for manufacturing image sensors and for forming test key 有权
标题翻译：用于制造图像传感器的晶片，用于缺陷检查的测试键布局，以及用于制造图像传感器和形成测试键的方法
公开(公告)号：US08003983B2
公开(公告)日：2011-08-23
申请号：US11379229
申请日：2006-04-19
申请人： Cheng-Hung Yu
发明人： Cheng-Hung Yu
IPC分类号： H01L23/544
CPC分类号： H01L27/14627
摘要： A wafer for manufacturing image sensors is disclosed. The wafer includes an image sensor and a test key. The image sensor includes a plurality of micro-lenses; the test key includes a plurality of micro-lens samples for defects inspection. The arrangement of the micro-lens samples on the test key is substantially different from the arrangement of the micro-lenses on the image sensor. The arrangement of the micro-lens samples on the test key allows defects inspection to become less complicated.
摘要翻译：公开了一种用于制造图像传感器的晶片。晶片包括图像传感器和测试键。图像传感器包括多个微透镜; 测试键包括用于缺陷检查的多个微透镜样本。微透镜样品在测试键上的布置与图像传感器上的微透镜的布置显着不同。微透镜样品在测试键上的布置使得缺陷检查变得不那么复杂。

7. 发明授权

US07987589B2 Multilayer three-dimensional circuit structure and manufacturing method thereof 有权
标题翻译：多层三维电路结构及其制造方法
公开(公告)号：US07987589B2
公开(公告)日：2011-08-02
申请号：US12333014
申请日：2008-12-11
申请人： Han-Pei Huang , Cheng-Hung Yu
发明人： Han-Pei Huang , Cheng-Hung Yu
IPC分类号： H05K3/02
CPC分类号： H05K3/4644 , B33Y10/00 , B33Y80/00 , H05K1/0284 , H05K3/046 , H05K3/06 , H05K3/185 , H05K3/205 , H05K3/386 , H05K2201/0236 , H05K2201/09118 , H05K2203/0108 , H05K2203/013 , H05K2203/107 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49165
摘要： A multilayer three-dimensional circuit structure and a manufacturing method thereof are provided in the present invention. The manufacturing method includes following steps. First, a three-dimensional insulating structure is provided. A first three-dimensional circuit structure is then formed on a surface of the three-dimensional insulating structure. Next, an insulating layer covering the first three-dimensional circuit structure is formed. Thereafter, a second three-dimensional circuit structure is formed on the insulating layer. Subsequently, at least a conductive via penetrating the insulating layer is formed for electrically connecting the second three-dimensional circuit structure and the first three-dimensional circuit structure.
摘要翻译：本发明提供了一种多层三维电路结构及其制造方法。制造方法包括以下步骤。首先，提供三维绝缘结构。然后在三维绝缘结构的表面上形成第一三维电路结构。接下来，形成覆盖第一三维电路结构的绝缘层。此后，在绝缘层上形成第二三维电路结构。随后，至少形成了穿过绝缘层的导电通孔，用于电连接第二三维电路结构和第一三维电路结构。

8. 发明申请

US20110023297A1 MULTI-LAYERED PRINTED CIRCUIT BOARD AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：多层印刷电路板及其制造方法
公开(公告)号：US20110023297A1
公开(公告)日：2011-02-03
申请号：US12902518
申请日：2010-10-12
申请人： Ming-Huan Yang , Chung-Wei Wang , Chia-Chi Wu , Chao-Kai Cheng , Tzyy-Jang Tseng , Chang-Ming Lee , Cheng-Po Yu , Cheng-Hung Yu
发明人： Ming-Huan Yang , Chung-Wei Wang , Chia-Chi Wu , Chao-Kai Cheng , Tzyy-Jang Tseng , Chang-Ming Lee , Cheng-Po Yu , Cheng-Hung Yu
IPC分类号： H05K3/10
CPC分类号： H05K3/182 , H05K3/389 , H05K3/421 , H05K3/422 , H05K3/426 , H05K3/4661 , H05K2203/013 , H05K2203/0565 , H05K2203/0709 , Y10T29/49155
摘要： A method for fabricating a double-sided or multi-layer printed circuit board (PCB) by ink jet printing that includes providing a substrate, forming a first self-assembly membrane (SAM) on at least one side of the substrate, forming a non-adhesive membrane on the first SAM, forming at least one microhole in the substrate, forming a second SAM on a surface of the microhole, providing catalyst particles on the at least one side of the substrate and on the surface of the microhole, and forming a catalyst circuit pattern on the substrate.
摘要翻译：一种通过喷墨印刷制造双面或多层印刷电路板（PCB）的方法，其包括提供基板，在所述基板的至少一侧上形成第一自组装膜（SAM），形成非 - 在第一SAM上形成粘合膜，在基底中形成至少一个微孔，在微孔的表面上形成第二SAM，在基底的至少一侧和微孔的表面上形成催化剂颗粒，并形成基板上的催化剂电路图案。

9. 发明申请

US20060176326A1 Fluid injector devices and methods for utilizing the same 审中-公开
标题翻译：流体注射器装置及其利用方法
公开(公告)号：US20060176326A1
公开(公告)日：2006-08-10
申请号：US11054671
申请日：2005-02-09
申请人： Chung-Cheng Chou , Tsung-Ping Hsu , Weng-Chen Liu , Cheng-Hung Yu , Shang-Shi Wu
发明人： Chung-Cheng Chou , Tsung-Ping Hsu , Weng-Chen Liu , Cheng-Hung Yu , Shang-Shi Wu
IPC分类号： B41J29/38
CPC分类号： B41J2/04588 , B41J2/04563 , B41J2/04565 , B41J2/0458
摘要： A fluid injector device with a plurality of heaters for bubble generation is provided. The resistance of each heater is measured and compared with a standard operating resistance. Output signal is adjusted to heaters with resistance exceeding the standard operating resistance.
摘要翻译：提供了具有用于产生气泡的多个加热器的流体注射器装置。测量每个加热器的电阻，并将其与标准工作电阻进行比较。输出信号被调整到具有超过标准工作电阻的电阻的加热器。

10. 发明授权

US06936386B2 Reticle alignment procedure 有权
标题翻译：标线校准程序
公开(公告)号：US06936386B2
公开(公告)日：2005-08-30
申请号：US10605677
申请日：2003-10-17
申请人： Cheng-Hung Yu
发明人： Cheng-Hung Yu
IPC分类号： G01B11/00 , G03C5/00 , G03F7/00 , G03F9/00 , H01L21/00 , H01L21/027
CPC分类号： G03F9/7011 , G03F9/7019 , G03F9/7088
摘要： A semiconductor wafer has at least one pre-layer on-wafer alignment mark (pre-layer on-wafer AM) on a top surface of the semiconductor wafer. A baseline check (BCHK) is performed to align a current-layer reticle AM on a current-layer reticle with the pre-layer on-wafer AM. By capturing and comparing signals of the current-layer reticle AM and the pre-layer on-wafer AM, a corresponding coordinate of the current-layer reticle to the semiconductor wafer is calibrated. Finally, a lithography process is performed to transfer the layout of the current-layer reticle AM to the top surface of the semiconductor wafer to form a corresponding current-layer on-wafer AM.
摘要翻译：半导体晶片在半导体晶片的顶表面上具有至少一个晶片上对准标记（晶片上的预层）。执行基线检查（BCHK）以将当前层掩模版上的当前层标线AM与晶片上的AM前层对准。通过捕获和比较当前层标线AM和晶片AM上的晶片AM的信号，校准当前层掩模版对半导体晶片的对应坐标。最后，进行光刻处理以将当前层标线AM的布局转移到半导体晶片的顶表面以形成相应的晶片上的电流层AM。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式