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1. 发明申请

US20110227146A1 POWER MOS TRANSISTOR DEVICE 有权
标题翻译：功率MOS晶体管器件
公开(公告)号：US20110227146A1
公开(公告)日：2011-09-22
申请号：US13129516
申请日：2008-11-27
申请人： Jean Michel Reynes , Beatrice Bernoux , Rene Escoffier , Pierre Jalbaud , Ivana Deram
发明人： Jean Michel Reynes , Beatrice Bernoux , Rene Escoffier , Pierre Jalbaud , Ivana Deram
IPC分类号： H01L27/06
CPC分类号： H01L29/7808 , H01L24/02 , H01L24/05 , H01L29/0696 , H01L29/1095 , H01L29/7802 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/4813 , H01L2224/4847 , H01L2224/49171 , H01L2924/01079 , H01L2924/12036 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/30107 , H01L2924/3011 , H01L2924/00015 , H01L2924/00
摘要： A transistor power switch device comprising a semiconductor body presenting opposite first and second faces, an array of vertical field-effect transistor elements for carrying current between the first and second faces, is provided. The array of transistor elements comprises at the first face an array of source regions of a first semiconductor type, at least one body region of a second semiconductor type opposite to the first type interposed between the source regions and the second face, at least one control electrode for switchably controlling flow of the current through the second transistor region, and a conductive layer contacting the source regions and insulated from the control electrode by at least one insulating layer.
摘要翻译：一种晶体管功率开关器件，包括具有相对的第一和第二面的半导体本体，用于在第一和第二面之间承载电流的垂直场效应晶体管元件阵列。晶体管元件的阵列在第一面上包括第一半导体类型的源极区域阵列，与源极区域和第二面部之间插入的第一类型相反的第二半导体类型的至少一个体区域，至少一个控制器用于可切换地控制通过第二晶体管区域的电流的电极，以及与源极区域接触并通过至少一个绝缘层与控制电极绝缘的导电层。

2. 发明授权

US08604560B2 Power MOS transistor device 有权
标题翻译：功率MOS晶体管器件
公开(公告)号：US08604560B2
公开(公告)日：2013-12-10
申请号：US13129516
申请日：2008-11-27
申请人： Jean Michel Reynes , Beatrice Bernoux , Rene Escoffier , Pierre Jalbaud , Ivana Deram
发明人： Jean Michel Reynes , Beatrice Bernoux , Rene Escoffier , Pierre Jalbaud , Ivana Deram
IPC分类号： H01L27/088
CPC分类号： H01L29/7808 , H01L24/02 , H01L24/05 , H01L29/0696 , H01L29/1095 , H01L29/7802 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/4813 , H01L2224/4847 , H01L2224/49171 , H01L2924/01079 , H01L2924/12036 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/30107 , H01L2924/3011 , H01L2924/00015 , H01L2924/00
摘要： A transistor power switch device comprising a semiconductor body presenting opposite first and second faces, an array of vertical field-effect transistor elements for carrying current between the first and second faces is provided. The array of transistor elements comprises at the first face an array of source regions of a first semiconductor type, at least one body region of a second semiconductor type opposite to the first type interposed between the source regions and the second face, at least one control electrode for switchably controlling flow of the current through the second transistor region, and a conductive layer contacting the source regions and insulated from the control electrode by at least one insulating layer.
摘要翻译：一种晶体管功率开关器件，包括具有相对的第一和第二面的半导体本体，提供用于在第一和第二面之间承载电流的垂直场效应晶体管元件阵列。晶体管元件的阵列在第一面上包括第一半导体类型的源极区域阵列，与源极区域和第二面部之间插入的第一类型相反的第二半导体类型的至少一个体区域，至少一个控制器用于可切换地控制通过第二晶体管区域的电流的电极，以及与源极区域接触并通过至少一个绝缘层与控制电极绝缘的导电层。

3. 发明授权

US08530953B2 Power MOS transistor device and switch apparatus comprising the same 有权
标题翻译：功率MOS晶体管器件及其开关装置
公开(公告)号：US08530953B2
公开(公告)日：2013-09-10
申请号：US13129505
申请日：2008-11-27
申请人： Jean Michel Reynes , Beatrice Bernoux , Rene Escoffier , Pierre Jalbaud , Ivana Deram
发明人： Jean Michel Reynes , Beatrice Bernoux , Rene Escoffier , Pierre Jalbaud , Ivana Deram
IPC分类号： H01L29/788
CPC分类号： H01L29/7808 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L29/0696 , H01L29/1095 , H01L29/7802 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/45014 , H01L2224/45124 , H01L2224/4813 , H01L2224/48137 , H01L2224/4847 , H01L2224/49171 , H01L2924/01005 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/12036 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00014
摘要： A transistor power switch device comprising an array of vertical transistor elements for carrying current between the first and second faces of a semiconductor body and a vertical avalanche diode electrically in parallel with the array of vertical transistors. The array of transistor elements includes at the first face an array of source regions of a first semiconductor type, at least one p region of a second semiconductor type opposite to the first type interposed between the source regions and the second face, at least one control electrode for switchably controlling flow of the current through the p region, and a conductive layer contacting the source regions and insulated from the control electrode. The vertical avalanche diode is configured to conduct breakdown current between the first and second faces in the off state of the device and having a first current carrying diode region of the second semiconductor type in contact with the first face and with the conductive layer and a second semiconductor region of the first semiconductor type electrically connected with the second face.
摘要翻译：一种晶体管功率开关装置，包括用于在半导体主体的第一和第二面之间承载电流的垂直晶体管元件阵列和与垂直晶体管阵列电并联的垂直雪崩二极管阵列。晶体管元件阵列在第一面上包括第一半导体类型的源区阵列，插入在源区和第二面之间的与第一类型相反的第二半导体类型的至少一个p区，至少一个控制用于切换控制通过p区域的电流的电极的电极，以及与源极区域接触并与控制电极绝缘的导电层。垂直雪崩二极管被配置为在器件的断开状态下在第一和第二面之间导通击穿电流，并且具有与第一面接触的第二半导体类型的第一载流二极管区和导电层，与第二面电连接的第一半导体类型的半导体区域。

4. 发明授权

US07955929B2 Method of forming a semiconductor device having an active area and a termination area 有权
标题翻译：形成具有有源区和终端区的半导体器件的方法
公开(公告)号：US07955929B2
公开(公告)日：2011-06-07
申请号：US12522036
申请日：2007-01-10
申请人： Evgueniy Stefanov , Ivana Deram , Jean-Michel Reynes
发明人： Evgueniy Stefanov , Ivana Deram , Jean-Michel Reynes
IPC分类号： H01L21/336 , H01L21/425
CPC分类号： H01L29/66719 , H01L29/0623 , H01L29/0634 , H01L29/42372 , H01L29/66712 , H01L29/7395 , H01L29/7811 , H01L29/8083
摘要： A method of forming a semiconductor device having an active area and a termination area surrounding the active area comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate and forming a mask layer over the semiconductor layer. The mask layer outlines at least two portions of a surface of the semiconductor layer: a first outlined portion outlining a floating region in the active area and a second outlined portion outlining a termination region in the termination area. Semiconductor material of a second conductivity type is provided to the first and second outlined portions so as to provide a floating region of the second conductivity type buried in the semiconductor layer in the active area and a first termination region of the second conductivity type buried in the semiconductor layer in the termination area of the semiconductor device.
摘要翻译：形成具有有源区域和围绕有源区域的端接区域的半导体器件的方法包括提供半导体衬底，在半导体衬底上提供第一导电类型的半导体层，并在半导体层上形成掩模层。掩模层概述半导体层的表面的至少两部分：概述有源区域中的浮动区域的第一轮廓部分和概述终止区域中的终止区域的第二轮廓部分。将第二导电类型的半导体材料提供给第一和第二轮廓部分，以便提供掩埋在有源区域中的半导体层中的第二导电类型的浮动区域和埋在第二导电类型中的第二导电类型的第一端接区域半导体器件的端接区域中的半导体层。

5. 发明申请

US20100001344A1 SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及形成半导体器件的方法
公开(公告)号：US20100001344A1
公开(公告)日：2010-01-07
申请号：US12522036
申请日：2007-01-10
申请人： Evgueniy Stefanov , Ivana Deram , Jean-Michel Reynes
发明人： Evgueniy Stefanov , Ivana Deram , Jean-Michel Reynes
IPC分类号： H01L29/78 , H01L21/22
CPC分类号： H01L29/66719 , H01L29/0623 , H01L29/0634 , H01L29/42372 , H01L29/66712 , H01L29/7395 , H01L29/7811 , H01L29/8083
摘要： A method of forming a semiconductor device having an active area and a termination area surrounding the active area comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate and forming a mask layer over the semiconductor layer. The mask layer outlines at least two portions of a surface of the semiconductor layer: a first outlined portion outlining a floating region in the active area and a second outlined portion outlining a termination region in the termination area. Semiconductor material of a second conductivity type is provided to the first and second outlined portions so as to provide a floating region of the second conductivity type buried in the semiconductor layer in the active area and a first termination region of the second conductivity type buried in the semiconductor layer in the termination area of the semiconductor device.
摘要翻译：形成具有有源区域和围绕有源区域的端接区域的半导体器件的方法包括提供半导体衬底，在半导体衬底上提供第一导电类型的半导体层，并在半导体层上形成掩模层。掩模层概述半导体层的表面的至少两部分：概述有源区域中的浮动区域的第一轮廓部分和概述终止区域中的终止区域的第二轮廓部分。将第二导电类型的半导体材料提供给第一和第二轮廓部分，以便提供掩埋在有源区域中的半导体层中的第二导电类型的浮动区域和埋在第二导电类型中的第二导电类型的第一端接区域半导体器件的端接区域中的半导体层。

6. 发明授权

US08004049B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08004049B2
公开(公告)日：2011-08-23
申请号：US11574478
申请日：2004-08-31
申请人： Jean-Michel Reynes , Stephane Alves , Ivana Deram , Blandino Lopes , Joel Margheritta , Frederico Morancho
发明人： Jean-Michel Reynes , Stephane Alves , Ivana Deram , Blandino Lopes , Joel Margheritta , Frederico Morancho
IPC分类号： H01L27/088
CPC分类号： H01L29/7802 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/0878
摘要： A device includes an array of cells, the source regions of the individual cells comprising a plurality of source region branches each extending towards a source region branch of an adjacent cell, the base regions of the individual cells comprising a corresponding plurality of base region branches merging together to form a single base region surrounding the source regions. The junctions between the merged base region and the drain region define rounded current conduction path areas for the on-state of the device between adjacent cells. Floating voltage regions of opposite conductivity type to the drain region are buried in the substrate beneath the merged base region. The features of the floating voltage regions define rings of the opposite conductivity type to the drain region that surround the current conduction paths of respective cells. The floating voltage regions include respective islands situated within the current conduction paths.
摘要翻译：一种设备包括单元阵列，各个单元的源区域包括多个源区域分支，每个源区域分支延伸到相邻单元的源区域分支，各个单元的基区包括对应的多个基本区域分支合并一起形成围绕源区域的单个碱基区域。合并的基极区域和漏极区域之间的结界定义用于相邻单元之间的器件的导通状态的圆形电流传导路径区域。与漏极区相反的导电类型的浮动电压区域埋在合并的基极区域下面的衬底中。浮动电压区域的特征限定环绕相应电池的电流传导路径的漏极区域的相反导电类型的环。浮置电压区域包括位于电流传导路径内的相应的岛。

7. 发明授权

US07432145B2 Power semiconductor device with a base region and method of manufacturing same 有权
标题翻译：具有基极区域的功率半导体器件及其制造方法
公开(公告)号：US07432145B2
公开(公告)日：2008-10-07
申请号：US10518158
申请日：2003-06-10
申请人： Jean-Michel Reynes , Ivana Deram , Adeline Feybesse
发明人： Jean-Michel Reynes , Ivana Deram , Adeline Feybesse
IPC分类号： H01L21/337
CPC分类号： H01L29/7802 , H01L29/0696
摘要： A low on-state resistance power semiconductor device has a shape and an arrangement that increase the channel density and the breakdown voltage The power semiconductor device comprises a plurality of individual cells formed on a semiconductor substrate (62). Each individual cell comprises a plurality of radially extending branches (80) having source regions (37) within base regions (36). The plurality of individual cells are arranged such that at least one branch of each cell extends towards at least one branch of an adjacent cell and wherein the base region (36) of the extending branches merge together to form a single and substantially uniformly doped base region (36) surrounding drain islands (39) at the surface of the semiconductor substrate (62).
摘要翻译：低导通电阻功率半导体器件具有增加沟道密度和击穿电压的形状和布置。功率半导体器件包括形成在半导体衬底（62）上的多个单独电池。每个单个电池包括在基极区域（36）内具有源极区（37）的多个径向延伸的分支（80）。多个单个单元被布置成使得每个单元的至少一个分支朝向相邻单元的至少一个分支延伸，并且其中延伸分支的基极区域（36）合并在一起以形成单个且基本上均匀掺杂的基极区域（36）围绕在半导体衬底（62）的表面处的漏极岛（39）。

8. 发明申请

US20060145252A1 Power semiconductor device and method of manufacturing the same 有权
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US20060145252A1
公开(公告)日：2006-07-06
申请号：US10518158
申请日：2003-06-10
申请人： Jean-Michel Reynes , Ivana Deram , Adeline Feybesse
发明人： Jean-Michel Reynes , Ivana Deram , Adeline Feybesse
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L29/0696
摘要： A low on-state resistance power semiconductor device has a shape and an arrangement that increase the channel density and the breakdown voltage. The power semiconductor device comprises a plurality of individual cells formed on a semiconductor substrate (62). Each individual cell comprises a plurality of radially extending branches (80) having source regions (37) within base regions (36). The plurality of individual cells are arranged such that at least one branch of each cell extends towards at least one branch of an adjacent cell and wherein the base region (36) of the extending branches merge together to form a single and substantially uniformly doped base region (36) surrounding drain islands (39) at the surface of the semiconductor substrate (62).
摘要翻译：低导通电阻功率半导体器件具有增加沟道密度和击穿电压的形状和布置。功率半导体器件包括形成在半导体衬底（62）上的多个单独电池。每个单个电池包括在基极区域（36）内具有源极区（37）的多个径向延伸的分支（80）。多个单个单元被布置成使得每个单元的至少一个分支朝向相邻单元的至少一个分支延伸，并且其中延伸分支的基极区域（36）合并在一起以形成单个且基本上均匀掺杂的基极区域（36）围绕在半导体衬底（62）的表面处的漏极岛（39）。

9. 发明申请

US20090014792A1 POWER SEMICONDUCTOR DEVICE 有权
标题翻译：功率半导体器件
公开(公告)号：US20090014792A1
公开(公告)日：2009-01-15
申请号：US11574478
申请日：2004-08-31
申请人： Jean-Michel Reynes , Stephane Alves , Ivana Deram , Blandino Lopes , Joel Margheritta , Frederic Morancho
发明人： Jean-Michel Reynes , Stephane Alves , Ivana Deram , Blandino Lopes , Joel Margheritta , Frederic Morancho
IPC分类号： H01L47/00
CPC分类号： H01L29/7802 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/0878
摘要： A power semiconductor device comprising an array of cells distributed over a surface of a substrate, the source regions of the individual cells of the array comprising a plurality of source region branches each extending laterally outwards towards at least one source region branch of an adjacent cell and presenting juxtaposed ends, the base regions of the individual cells of the array comprising a corresponding plurality of base region branches merging together adjacent and between the juxtaposed ends of the source region branches to form a single base region surrounding the source regions of the individual cells of the array in the substrate. The junctions between the merged base region and the drain region are solely concave laterally and define rounded current conduction path areas for the on-state of the device between adjacent cells that are depleted in the off-state of the device to block flow of current from the source regions to the drain electrode. Floating voltage regions of opposite conductivity type to the drain region are buried in the substrate beneath the merged base region and present features corresponding to and juxtaposed with features of the merged base region in each cell so that the voltage of the floating voltage regions tends to the voltage of the source regions when depletion layers blocking the current conduction paths reach the floating voltage regions, whereby to enhance the development of the depletion layers. The features of the floating voltage regions define rings of the opposite conductivity type to the drain region that surround the current conduction paths of respective cells. The floating voltage regions include respective islands situated within the current conduction paths.
摘要翻译：一种功率半导体器件，包括分布在衬底表面上的单元阵列，所述阵列的各个单元的源极区域包括多个源区域支路，每个源极区域分支向邻近小区的至少一个源极区域横向向外延伸，呈现并置的端部，阵列的各个单元的基极区域包括在源极区域的相邻端和并置端之间并联在一起的对应的多个基极区域分支，以形成围绕各个单元的源极区域的单个基极区域阵列在基片中。合并的基极区域和漏极区域之间的结点仅仅是侧向凹进的，并且限定用于在器件断开状态下耗尽的器件的导通状态的圆形电流传导路径区域，以阻止电流从源极区到漏电极。与漏极区相反的导电类型的浮动电压区域被埋在合并的基极区域下面的衬底中，并且呈现出与每个单元中合并的基极区域的特征对应并并置的特征，使得浮动电压区域的电压趋向于阻挡电流传导路径的耗尽层到达浮动电压区域时的源极区域的电压，从而增强耗尽层的发展。浮动电压区域的特征限定环绕相应电池的电流传导路径的漏极区域的相反导电类型的环。浮置电压区域包括位于电流传导路径内的相应的岛。

10. 发明授权

US06773977B1 Method of forming a diode for integration with a semiconductor device and method of forming a transistor device having an integrated diode 失效
标题翻译：形成用于与半导体器件集成的二极管的方法和形成具有集成二极管的晶体管器件的方法
公开(公告)号：US06773977B1
公开(公告)日：2004-08-10
申请号：US09715748
申请日：2000-11-17
申请人： Jean-Michel Reynes , Ivana Deram , Evgueniy Stefanov
发明人： Jean-Michel Reynes , Ivana Deram , Evgueniy Stefanov
IPC分类号： H01L218234
CPC分类号： H01L29/66719 , H01L27/0629 , H01L29/66136 , H01L29/66712 , H01L29/7804
摘要： The present invention relates to a method of forming a diode (2) for integration with a semiconductor device comprising the steps of providing a layer (4) of semiconductor material, forming a dielectric layer (6) over the layer of semiconductor material, introducing a first conductivity type dopant into the dielectric layer (6), forming a semi-conductive layer (8) over the dielectric layer (6), introducing a second conductivity type dopant into a first region (12) of the semi-conductive layer and re-distributing the first conductivity type dopant from the dielectric layer (6) into the semi-conductive layer (8) so as to form a second region (18) of the first conductivity type dopant in the semi-conductive layer (8), the second region (18) being adjacent the first region (12) so as to provide a P/N junction of the diode (2).
摘要翻译：本发明涉及一种形成与半导体器件集成的二极管（2）的方法，包括以下步骤：提供半导体材料层（4），在半导体材料层上形成介电层（6），引入在所述电介质层（6）中形成第一导电型掺杂剂，在所述电介质层（6）上形成半导电层（8），将第二导电类型掺杂剂引入所述半导体层的第一区域（12）将所述第一导电型掺杂剂从所述介电层（6）分布到所述半导体层（8）中，以在所述半导电层（8）中形成所述第一导电类型掺杂剂的第二区域（18），第二区域（18）与第一区域（12）相邻，以便提供二极管（2）的P / N结。

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