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1. 发明授权

US07620931B2 Method of adding fabrication monitors to integrated circuit chips 失效
标题翻译：将制造监控器添加到集成电路芯片的方法
公开(公告)号：US07620931B2
公开(公告)日：2009-11-17
申请号：US11859890
申请日：2007-09-24
申请人： James W. Adkisson , Greg Bazan , John M. Cohn , Matthew S. Grady , Thomas G. Sopchak , David P. Vallett
发明人： James W. Adkisson , Greg Bazan , John M. Cohn , Matthew S. Grady , Thomas G. Sopchak , David P. Vallett
IPC分类号： G06F17/50
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.
摘要翻译：一种用于设计的集成电路，方法和系统以及制造集成电路的方法。该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状，集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

2. 发明授权

US07323278B2 Method of adding fabrication monitors to integrated circuit chips 有权
标题翻译：将制造监控器添加到集成电路芯片的方法
公开(公告)号：US07323278B2
公开(公告)日：2008-01-29
申请号：US11687731
申请日：2007-03-19
申请人： James W. Adkisson , Greg Bazan , John M. Cohn , Matthew S. Grady , Thomas G. Sopchak , David P. Vallett
发明人： James W. Adkisson , Greg Bazan , John M. Cohn , Matthew S. Grady , Thomas G. Sopchak , David P. Vallett
IPC分类号： G03F9/00 , G03C5/00
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.
摘要翻译：一种用于设计的集成电路，方法和系统以及制造集成电路的方法。该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状，集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

3. 发明授权

US07194706B2 Designing scan chains with specific parameter sensitivities to identify process defects 失效
标题翻译：设计具有特定参数灵敏度的扫描链，以识别过程缺陷
公开(公告)号：US07194706B2
公开(公告)日：2007-03-20
申请号：US10710642
申请日：2004-07-27
申请人： James W. Adkisson , Greg Bazan , John M. Cohn , Matthew S. Grady , Leendert M. Huisman , Mark D. Jaffe , Phillip J. Nigh , Leah M. P. Pastel , Thomas G. Sopchak , David E. Sweenor , David P. Vallett
发明人： James W. Adkisson , Greg Bazan , John M. Cohn , Matthew S. Grady , Leendert M. Huisman , Mark D. Jaffe , Phillip J. Nigh , Leah M. P. Pastel , Thomas G. Sopchak , David E. Sweenor , David P. Vallett
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G01R31/31855 , G01R31/318586 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip. The model is provided as input parameters to a global placement and wiring program used to lay out the scan chains. Test data on the chip is then analyzed to determine and isolate systematic yield problems denoted by attributes of a statistically significant failing population of a specific type of scan chain.
摘要翻译：公开了一种用于设计具有特定参数灵敏度的集成电路芯片中的扫描链的方法，以识别导致测试失败和芯片产量损失的制造工艺缺陷。集成电路芯片中的扫描路径的组成被偏置以允许它们也用作产品过程监视器。该方法增加了分组约束，使得扫描链偏置以在可能的情况下具有共同的锁存单元使用，并且还偏置小区路由以将扫描链路由限制到用于互连的给定受限金属层。该方法组合了对过程变化或完整性敏感的锁存器设计参数列表，并且制定了扫描链设计的计划，该计划确定了扫描链的数量和长度。基于产量和过程完整性的当前状态来制定扫描链设计的模型，其中为芯片上的特定扫描链选择具有主要灵敏度的某些锁存器设计。该模型作为输入参数提供给用于布置扫描链的全局放置和布线程序。然后对芯片上的测试数据进行分析，以确定和分离由特定类型的扫描链的统计学显着失败群体的属性表示的系统产量问题。

4. 发明授权

US07240322B2 Method of adding fabrication monitors to integrated circuit chips 有权
标题翻译：将制造监控器添加到集成电路芯片的方法
公开(公告)号：US07240322B2
公开(公告)日：2007-07-03
申请号：US10907494
申请日：2005-04-04
申请人： James W. Adkisson , Greg Bazan , John M. Cohn , Matthew S. Grady , Thomas G. Sopchak , David P. Vallett
发明人： James W. Adkisson , Greg Bazan , John M. Cohn , Matthew S. Grady , Thomas G. Sopchak , David P. Vallett
IPC分类号： G06F17/50
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.
摘要翻译：一种用于设计的集成电路，方法和系统以及制造集成电路的方法。该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状，集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

5. 发明授权

US07089514B2 Defect diagnosis for semiconductor integrated circuits 失效
标题翻译：半导体集成电路缺陷诊断
公开(公告)号：US07089514B2
公开(公告)日：2006-08-08
申请号：US10710879
申请日：2004-08-10
申请人： James W. Adkisson , Greg Bazan , John M. Cohn , Francis Gravel , Leendert M. Huisman , Phillip J. Nigh , Leah M. P. Pastel , Kenneth Rowe , Thomas G. Sopchak , David E. Sweenor
发明人： James W. Adkisson , Greg Bazan , John M. Cohn , Francis Gravel , Leendert M. Huisman , Phillip J. Nigh , Leah M. P. Pastel , Kenneth Rowe , Thomas G. Sopchak , David E. Sweenor
IPC分类号： G06F17/50
CPC分类号： G01R31/31718 , G01R31/318342
摘要： A method for defect diagnosis of semiconductor chip. The method comprises the steps of (a) identifying M design structures and N physical characteristics of the circuit design, wherein M and N are positive integers, wherein each design structure of the M design structures is testable as to pass or fail, and wherein each physical characteristic of the N physical characteristics is present in at least one design structure of the M design structures; (b) for each design structure of the M design structures of the circuit design, determining a fail rate and determining whether the fail rate is high or low; and (c) if every design structure of the M design structures in which a physical characteristic of the N physical characteristics is present has a high fail rate, then flagging the physical characteristic as being likely to contain at least a defect.
摘要翻译：一种半导体芯片缺陷诊断方法。该方法包括以下步骤：（a）识别电路设计的M个设计结构和N个物理特性，其中M和N是正整数，其中M个设计结构的每个设计结构可以通过或失败，并且其中每个 N物理特性的物理特性存在于M设计结构的至少一个设计结构中; （b）对于电路设计的M设计结构的每个设计结构，确定故障率并确定故障率是高还是低; 和（c）如果存在N个物理特性的物理特性的M设计结构的每个设计结构具有高故障率，则将物理特性标记为可能至少包含缺陷。

6. 发明授权

US07558999B2 Learning based logic diagnosis 有权
标题翻译：基于学习的逻辑诊断
公开(公告)号：US07558999B2
公开(公告)日：2009-07-07
申请号：US10709672
申请日：2004-05-21
申请人： James W. Adkisson , John M. Cohn , Leendert M. Huisman , Maroun Kassab , Leah M. Pfeifer Pastel , David E. Sweenor
发明人： James W. Adkisson , John M. Cohn , Leendert M. Huisman , Maroun Kassab , Leah M. Pfeifer Pastel , David E. Sweenor
IPC分类号： G01R31/28 , G06F11/00 , G11C29/00
CPC分类号： G06F11/2252 , G06F11/261
摘要： A system and method for diagnosing a failure in an electronic device. A disclosed system comprises: a defect table that associates previously studied features with known failures; and a fault isolation system that compares an inputted set of suspected faulty device features with the previously studied features listed in the defect table in order to identify causes of the failure.
摘要翻译：一种用于诊断电子设备故障的系统和方法。所公开的系统包括：将先前研究的特征与已知故障相关联的缺陷表; 以及故障隔离系统，其将输入的可疑故障设备特征集合与缺陷表中列出的先前研究的特征进行比较，以识别故障原因。

7. 发明授权

US08723392B2 Saw filter having planar barrier layer and method of making 有权
标题翻译：具有平面阻挡层的锯片和制造方法
公开(公告)号：US08723392B2
公开(公告)日：2014-05-13
申请号：US13183977
申请日：2011-07-15
申请人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
发明人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
IPC分类号： H03H9/25
CPC分类号： H03H9/14538 , H03H3/08
摘要： Disclosed herein is a surface acoustic wave (SAW) filter and method of making the same. The SAW filter includes a piezoelectric substrate; a planar barrier layer disposed above the piezoelectric substrate, and at least one conductor buried in the piezoelectric substrate and the planar barrier layer.
摘要翻译：本文公开了一种表面声波（SAW）滤波器及其制造方法。 SAW滤波器包括压电基片; 设置在所述压电基板上方的平面阻挡层，以及埋设在所述压电基板和所述平面阻挡层中的至少一个导体。

8. 发明授权

US08716771B2 Anti-reflection structures for CMOS image sensors 有权
公开(公告)号：US08716771B2
公开(公告)日：2014-05-06
申请号：US13418706
申请日：2012-03-13
申请人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
发明人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
IPC分类号： H01L31/10 , H01L31/112
CPC分类号： H01L31/103 , H01L24/05 , H01L24/73 , H01L27/14603 , H01L27/1462 , H01L27/14627 , H01L27/14629 , H01L27/1464 , H01L27/14643 , H01L31/02165 , H01L31/0236 , H01L2224/04042 , H01L2224/05 , H01L2224/32225 , H01L2224/48227 , H01L2224/48464 , H01L2224/4847 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/01074 , H01L2924/12043 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/3025 , Y02E10/50 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.

9. 发明授权

US08673683B2 Graphene field effect transistor 有权
标题翻译：石墨烯场效应晶体管
公开(公告)号：US08673683B2
公开(公告)日：2014-03-18
申请号：US13492131
申请日：2012-06-08
申请人： James W. Adkisson , Thomas J. Dunbar , Jeffrey P. Gambino , Molly J. Leitch , Edward J. Nowak
发明人： James W. Adkisson , Thomas J. Dunbar , Jeffrey P. Gambino , Molly J. Leitch , Edward J. Nowak
IPC分类号： H01L51/40 , H01L21/8232 , H01L21/336
CPC分类号： H01L29/1606 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B32/186 , H01L27/1222 , H01L29/41733 , H01L29/42384 , H01L29/66045 , H01L29/66742 , H01L29/778 , H01L29/7786 , H01L29/785 , H01L29/78684 , H01L29/78696
摘要： Manufacturing a semiconductor structure including: forming a seed material on an insulator layer; forming a graphene field effect transistor (FET) on the seed material; and forming an air gap under the graphene FET by removing the seed material.
摘要翻译：制造半导体结构，包括：在绝缘体层上形成种子材料; 在种子材料上形成石墨烯场效应晶体管（FET）; 并通过除去种子材料在石墨烯FET下方形成气隙。

10. 发明授权

US08546230B2 Bipolar transistor with a collector having a protected outer edge portion for reduced based-collector junction capacitance and a method of forming the transistor 有权
标题翻译：具有集电器的双极晶体管具有受保护的外边缘部分，用于降低基极集电极结电容，以及形成晶体管的方法
公开(公告)号：US08546230B2
公开(公告)日：2013-10-01
申请号：US13296496
申请日：2011-11-15
申请人： James W. Adkisson , David L. Harame , Robert K. Leidy , Qizhi Liu
发明人： James W. Adkisson , David L. Harame , Robert K. Leidy , Qizhi Liu
IPC分类号： H01L21/331 , H01L29/66
CPC分类号： H01L29/732 , H01L29/7371
摘要： Disclosed are embodiments of a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a collector region having a protected upper edge portion for reduced base-collector junction capacitance Cbc. In the embodiments, a collector region is positioned laterally adjacent to a trench isolation region within a substrate. Mask layer(s) cover the trench isolation region and further extend laterally onto the edge portion of the collector region. A first section of an intrinsic base layer is positioned above a center portion of the collector region and a second section of the intrinsic base layer is positioned above the mask layer(s). During processing these mask layer(s) prevent divot formation in the upper corner of the trench isolation region at the isolation region-collector region interface and further limit dopant diffusion from a subsequently formed raised extrinsic base layer into the collector region.
摘要翻译：公开了晶体管（例如双极结型晶体管（BJT）或异质结双极晶体管（HBT））的实施例以及形成具有集电极区域的晶体管的方法，该集电极区域具有用于还原的基极 - 集电极结电容Cbc的受保护的上边缘部分。在实施例中，集电极区域位于衬底内侧向与沟槽隔离区域相邻的位置。掩模层覆盖沟槽隔离区域并且进一步横向延伸到收集器区域的边缘部分上。本征基极层的第一部分位于集电极区域的中心部分的上方，并且本征基极层的第二部分位于掩模层之上。在处理期间，这些掩模层防止在隔离区域 - 集电极区界面处的沟槽隔离区的上角部形成裂缝，并且进一步限制从随后形成的凸起的外在基极层到集电极区域的掺杂剂扩散。

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