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1. 发明授权

US08492816B2 Deep trench decoupling capacitor 有权
标题翻译：深沟槽去耦电容
公开(公告)号：US08492816B2
公开(公告)日：2013-07-23
申请号：US12685156
申请日：2010-01-11
申请人： James S. Nakos , Edmund J. Sprogis , Anthony K. Stamper
发明人： James S. Nakos , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L28/40 , H01L29/66181 , H01L29/945
摘要： Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a semiconductor structure includes a trench capacitor within a silicon substrate, the trench capacitor including: an outer trench extending into the silicon substrate; a dielectric liner layer in contact with the outer trench; a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench within the outer trench; and a silicide layer over a portion of the doped polysilicon layer, the silicide layer separating at least a portion of the contact from at least a portion of the doped polysilicon layer; and a contact having a lower surface abutting the trench capacitor, a portion of the lower surface not abutting the silicide layer.
摘要翻译：公开了用于形成硅化深沟槽去耦电容器的解决方案。一方面，半导体结构在硅衬底内包括沟槽电容器，所述沟槽电容器包括：延伸到硅衬底中的外沟槽; 介电衬垫层，与所述外沟槽接触; 所述掺杂多晶硅层在所述外部沟槽内形成内部沟槽; 以及在所述掺杂多晶硅层的一部分上的硅化物层，所述硅化物层将所述接触的至少一部分与所述掺杂多晶硅层的至少一部分分离; 以及具有与所述沟槽电容器邻接的下表面的接触件，所述下表面的一部分不邻接所述硅化物层。

2. 发明申请

US20110169131A1 DEEP TRENCH DECOUPLING CAPACITOR 有权
标题翻译：深层解压电容器
公开(公告)号：US20110169131A1
公开(公告)日：2011-07-14
申请号：US12685156
申请日：2010-01-11
申请人： James S. Nakos , Edmund J. Sprogis , Anthony K. Stamper
发明人： James S. Nakos , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L28/40 , H01L29/66181 , H01L29/945
摘要： Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a semiconductor structure includes a trench capacitor within a silicon substrate, the trench capacitor including: an outer trench extending into the silicon substrate; a dielectric liner layer in contact with the outer trench; a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench within the outer trench; and a silicide layer over a portion of the doped polysilicon layer, the silicide layer separating at least a portion of the contact from at least a portion of the doped polysilicon layer; and a contact having a lower surface abutting the trench capacitor, a portion of the lower surface not abutting the silicide layer.
摘要翻译：公开了用于形成硅化深沟槽去耦电容器的解决方案。一方面，半导体结构在硅衬底内包括沟槽电容器，所述沟槽电容器包括：延伸到硅衬底中的外沟槽; 介电衬垫层，与所述外沟槽接触; 所述掺杂多晶硅层在所述外部沟槽内形成内部沟槽; 以及在所述掺杂多晶硅层的一部分上的硅化物层，所述硅化物层将所述接触的至少一部分与所述掺杂多晶硅层的至少一部分分离; 以及具有与所述沟槽电容器邻接的下表面的接触件，所述下表面的一部分不邻接所述硅化物层。

3. 发明申请

US20120193790A1 ELECTROSTATIC CHUCKING OF AN INSULATOR HANDLE SUBSTRATE 有权
标题翻译：绝缘子手柄底座的静电切割
公开(公告)号：US20120193790A1
公开(公告)日：2012-08-02
申请号：US13444193
申请日：2012-04-11
申请人： Paul S. Andry , Edward C. Cooney, III , Edmund J. Sprogis , Anthony K. Stamper , Cornelia K. Tsang
发明人： Paul S. Andry , Edward C. Cooney, III , Edmund J. Sprogis , Anthony K. Stamper , Cornelia K. Tsang
IPC分类号： H01L23/498
CPC分类号： H01L24/10 , H01L23/5384 , H01L24/13 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/05684 , H01L2224/05686 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01327 , H01L2924/04953 , H01L2924/12044 , H01L2924/15311 , H01L2924/00 , H01L2924/00014 , H01L2924/049
摘要： A back of a dielectric transparent handle substrate is coated with a blanket conductive film or a mesh of conductive wires. A semiconductor substrate is attached to the transparent handle substrate employing an adhesive layer. The semiconductor substrate is thinned in the bonded structure to form a stack of the transparent handle substrate and the semiconductor interposer. The thinned bonded structure may be loaded into a processing chamber and electrostatically chucked employing the blanket conductive film or the mesh of conductive wires. The semiconductor interposer may be bonded to a semiconductor chip or a packaging substrate employing C4 bonding or intermetallic alloy bonding. Illumination of ultraviolet radiation to the adhesive layer is enabled, for example, by removal of the blanket conductive film or through the mesh so that the transparent handle substrate may be detached. The semiconductor interposer may then be bonded to a packaging substrate or a semiconductor chip.
摘要翻译：电介质透明手柄基板的背面涂覆有橡皮布导电膜或导电丝网。使用粘合剂层将半导体衬底附接到透明手柄衬底。半导体衬底在接合结构中变薄以形成透明手柄衬底和半导体插入器的堆叠。减薄的粘合结构可以被加载到处理室中并且使用橡皮布导电膜或导线的网状物静电夹持。半导体插入件可以结合到采用C4键合或金属间化合物键合的半导体芯片或封装衬底。照射紫外线到粘合剂层是可以实现的，例如，通过去除橡皮布传导膜或通过网格，使透明手柄基板可以分离。然后可以将半导体中介层结合到封装衬底或半导体芯片。

4. 发明申请

US20100025857A1 IC CHIP AND DESIGN STRUCTURE WITH THROUGH WAFER VIAS DISHING CORRECTION 有权
标题翻译：通过WAVER VIAS DISHING CORRECTION进行IC芯片和设计结构
公开(公告)号：US20100025857A1
公开(公告)日：2010-02-04
申请号：US12181467
申请日：2008-07-29
申请人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
发明人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01L23/48 , G06F9/45
CPC分类号： H01L21/76898 , H01L21/76838 , H01L21/7684
摘要： An IC chip and design structure having a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV. An IC chip may include a substrate; a through wafer via (TWV) extending through at least one first dielectric layer and into the substrate; a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV; and a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting the TWV contact.
摘要翻译：具有TWV触点的IC芯片和设计结构接触TWV并延伸穿过TWV上的第二介电层。 IC芯片可以包括基板; 穿过至少一个第一电介质层并进入衬底的贯通晶片通孔（TWV）; TWV触点接触TWV并延伸穿过TWV上的第二电介质层; 以及在所述第二电介质层上的第一金属布线层，所述第一金属布线层与所述TWV触点接触。

5. 发明申请

US20120137515A1 THROUGH WAFER VIAS WITH DISHING CORRECTION METHODS 有权
标题翻译：通过具有循环校正方法的WAVER VIAS
公开(公告)号：US20120137515A1
公开(公告)日：2012-06-07
申请号：US13369414
申请日：2012-02-09
申请人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
发明人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01K3/10
CPC分类号： H01L21/76898 , H01L21/76838 , H01L21/7684 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming through wafer vias (TWVs) and standard contacts in two separate processes to prevent copper first metal layer puddling and shorts are presented. In one embodiment, a method may include forming a TWV into a substrate and a first dielectric layer over the substrate; forming a second dielectric layer over the substrate and the TWV; forming, through the second dielectric layer, at least one contact to the TWV and at least one contact to other structures over the substrate; and forming a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting at least one of the contacts.
摘要翻译：提出了通过晶片通孔（TWV）和标准触点在两个单独的工艺中形成以防止铜第一金属层挤压和短路的方法。在一个实施例中，一种方法可以包括将TWV形成到衬底上并且在衬底上形成第一介电层; 在所述衬底和所述TWV上形成第二电介质层; 通过所述第二电介质层形成至少一个接触到所述TWV和与所述衬底上的其它结构的至少一个接触; 以及在所述第二电介质层上形成第一金属布线层，所述第一金属布线层与所述触点中的至少一个接触。

6. 发明授权

US08166651B2 Through wafer vias with dishing correction methods 有权
标题翻译：通过具有凹陷校正方法的晶片通孔
公开(公告)号：US08166651B2
公开(公告)日：2012-05-01
申请号：US12181359
申请日：2008-07-29
申请人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
发明人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01K3/10 , H05K3/02 , H05K3/10 , H01L29/40
CPC分类号： H01L21/76898 , H01L21/76838 , H01L21/7684 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a through wafer via including forming the through wafer via (TWV) into a substrate and through a first dielectric layer over the substrate; planarizing the first dielectric layer using a chemical mechanical polish before forming a second dielectric layer; forming the second dielectric layer over the substrate and the TWV; forming at least one first contact through the second dielectric layer and to the TWV; forming at least one second contact through the second dielectric layer and the first dielectric layer directly and electrically connected to another structure upon the substrate; and forming a first metal wiring layer directly over the second dielectric layer, the first metal wiring layer directly and physically contacting the at least one first contact and the at least one second contact.
摘要翻译：一种形成贯穿晶片通孔的方法，包括通过（TWV）形成贯穿晶片进入衬底并穿过衬底上的第一介电层; 在形成第二电介质层之前，使用化学机械抛光平面化第一介电层; 在所述衬底和所述TWV上形成所述第二电介质层; 通过所述第二介电层和所述TWV形成至少一个第一接触; 通过所述第二电介质层和所述第一介电层形成至少一个第二接触，并且在所述衬底上直接电连接到另一结构; 以及直接在所述第二电介质层上方形成第一金属布线层，所述第一金属布线层直接地和物理地接触所述至少一个第一触点和所述至少一个第二触点。

7. 发明授权

US08136084B2 Arranging through silicon vias in IC layout 有权
标题翻译：在IC布局中排列硅通孔
公开(公告)号：US08136084B2
公开(公告)日：2012-03-13
申请号：US12555981
申请日：2009-09-09
申请人： Donald R. Dean, Jr. , Peter J. Lindgren , Glen L. Miles , Edmund J. Sprogis , Anthony K. Stamper
发明人： Donald R. Dean, Jr. , Peter J. Lindgren , Glen L. Miles , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： G06F17/52
CPC分类号： H01L21/76898 , G06F17/5072
摘要： A portion of an IC layout that includes a plurality of through silicon vias (TSVs) is evaluated to identify linearly aligned TSVs. The portion of the IC layout is modified to reduce a number of the linearly aligned TSVs, resulting in less wafer breakage.
摘要翻译：评估包括多个贯穿硅通孔（TSV）的IC布局的一部分以识别线性对准的TSV。修改IC布局的部分以减少多个线性对齐的TSV，导致较少的晶片断裂。

8. 发明申请

US20110177435A1 Photomasks having sub-lithographic features to prevent undesired wafer patterning 审中-公开
标题翻译：具有亚光刻特征以防止不期望的晶片图案化的光掩模
公开(公告)号：US20110177435A1
公开(公告)日：2011-07-21
申请号：US12690312
申请日：2010-01-20
申请人： Russell T. Herrin , Edmund J. Sprogis , Anthony K. Stamper
发明人： Russell T. Herrin , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： G03F1/00
CPC分类号： G03F1/42 , G03F1/36 , G03F1/38
摘要： A photomask that is used as a light filter in an exposure system is made of at least one layer of material comprising one or more transparent regions and one or more non-transparent regions. The difference between the transparent regions and the non-transparent regions defines the features that will be illuminated by the exposure system on a photoresist that will be exposed using the exposure system. The features comprise one or more device shapes and at least one sub-lithographic shape that will be exposed upon the photoresist. The sub-lithographic shape has an sub-lithographic shape size that is limited in such a way that the sub-lithographic shape causes a physical change only in a surface of the photoresist. Therefore, because the sub-lithographic shape is so small, it avoids forming an opening through the photoresist after the photoresist is developed and only causes a change on the surface of the photoresist.
摘要翻译：在曝光系统中用作滤光器的光掩模由包括一个或多个透明区域和一个或多个不透明区域的至少一层材料制成。透明区域和不透明区域之间的差异限定了曝光系统将在将使用曝光系统曝光的光刻胶上照亮的特征。这些特征包括一个或多个器件形状和将被暴露在光刻胶上的至少一个亚光刻形状。亚光刻形状具有亚光刻形状尺寸，其受到限制，使得亚光刻形状仅在光致抗蚀剂的表面引起物理变化。因此，由于亚光刻形状如此之小，因此避免了在光致抗蚀剂显影之后通过光致抗蚀剂形成开口，并且仅引起光致抗蚀剂表面的变化。

9. 发明申请

US20110057319A1 ARRANGING THROUGH SILICON VIAS IN IC LAYOUT 有权
标题翻译：通过IC布局中的硅胶排列
公开(公告)号：US20110057319A1
公开(公告)日：2011-03-10
申请号：US12555981
申请日：2009-09-09
申请人： Donald R. Dean, JR. , Peter J. Lindgren , Glen L. Miles , Edmund J. Sprogis , Anthony K. Stamper
发明人： Donald R. Dean, JR. , Peter J. Lindgren , Glen L. Miles , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01L23/48 , G06F17/50
CPC分类号： H01L21/76898 , G06F17/5072
摘要： A portion of an IC layout that includes a plurality of through silicon vias (TSVs) is evaluated to identify linearly aligned TSVs. The portion of the IC layout is modified to reduce a number of the linearly aligned TSVs, resulting in less wafer breakage.
摘要翻译：评估包括多个贯穿硅通孔（TSV）的IC布局的一部分以识别线性对准的TSV。修改IC布局的部分以减少多个线性对齐的TSV，导致较少的晶片断裂。

10. 发明申请

US20100019346A1 IC HAVING FLIP CHIP PASSIVE ELEMENT AND DESIGN STRUCTURE 审中-公开
标题翻译： IC具有FLIP芯片被动元件和设计结构
公开(公告)号：US20100019346A1
公开(公告)日：2010-01-28
申请号：US12180810
申请日：2008-07-28
申请人： Mete Erturk , Edmund J. Sprogis , Anthony K. Stamper
发明人： Mete Erturk , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01L29/00
CPC分类号： H01L24/91 , H01F17/0006 , H01F27/027 , H01L23/645 , H01L24/16 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/94 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/056 , H01L2224/16 , H01L2224/16145 , H01L2224/45124 , H01L2224/48091 , H01L2224/48463 , H01L2224/73257 , H01L2224/81801 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19104 , H01L2924/30105 , H01L2224/05599 , H01L2924/013 , H01L2924/00013 , H01L2224/05099 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： IC and design structure including various ways of raising a passive element such as an inductor off the surface of the substrate to improve the performance of the passive element are presented. A first wafer may be provided, and passive elements diced from a second wafer. The passive elements are flipped, and then aligned to be bonded on the first wafer such that the passive elements are raised a distance off the first wafer because of the presence of chip connections such as C4 solder bumps. A gap between the passive elements and the first wafer can be filled with underfill or air. If air is used, a hermetic seal around the gap can be created using chip connections such as C4 solder bumps or other known bonding means to seal the gap.
摘要翻译：提出了IC和设计结构，其中包括从基板表面起提高无源元件（如电感器）以提高无源元件的性能的各种方式。可以提供第一晶片，并且从第二晶片切割无源元件。无源元件翻转，然后对齐以接合在第一晶片上，使得无源元件由于存在诸如C4焊料凸块的芯片连接而离开第一晶片一段距离。无源元件和第一晶片之间的间隙可以用底部填充物或空气填充。如果使用空气，则可以使用诸如C4焊料凸块或其它已知的粘合装置之类的芯片连接来密封间隙来创建间隙周围的气密密封。

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