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1. 发明授权

US08025240B2 Radiant heat flooring system 有权
标题翻译：辐射热地板系统
公开(公告)号：US08025240B2
公开(公告)日：2011-09-27
申请号：US11550977
申请日：2006-10-19
申请人： James Keller
发明人： James Keller
IPC分类号： F24D3/14 , F24D3/12
CPC分类号： F24D3/127 , F24D3/142
摘要： A flooring system for radiant heating includes a top floor portion and a subfloor portion. The top portion is releasably connectable to the subfloor portion in a vertical direction substantially perpendicular to a walking surface of the top portion. The top portion includes a bottom side and top channel portion downwardly depending from the bottom side. The subfloor portion includes a top side and a bottom channel portion extending upwardly from the top side. The top channel portion and the bottom channel portion bound a channel for receiving a heating conduit. The channel extends longitudinally relative to the top floor portion and the subfloor portion.
摘要翻译：用于辐射加热的地板系统包括顶层部分和底层地板部分。顶部可在基本上垂直于顶部的行走表面的垂直方向上可释放地连接到底层地板部分。顶部包括从底侧向下悬垂的底侧和顶部通道部分。底层部分包括从顶侧向上延伸的顶侧和底通道部分。顶部通道部分和底部通道部分限定了用于接收加热导管的通道。通道相对于顶层部分和底层部分纵向延伸。

2. 发明授权

US07346078B2 Processing of received data within a multiple processor device 有权
标题翻译：处理多处理器设备内的接收数据
公开(公告)号：US07346078B2
公开(公告)日：2008-03-18
申请号：US10356324
申请日：2003-01-31
申请人： Manu Gulati , Laurent Moll , James Keller
发明人： Manu Gulati , Laurent Moll , James Keller
IPC分类号： H04J3/22
CPC分类号： G06F13/4247
摘要： A multiple processor device stores a stream of data as a plurality of data segments, which includes multiplexed data fragments from at least one of a plurality of virtual channels. The data segments that comprise the stream of data correspond to the multiplexed data fragments from the virtual channels. The multiple processor device then decodes at least one data segment in accordance with one of a plurality of transmission protocols to produce a decoded data segment. The multiple processor device then stores the decoded data segment to align it in accordance with a data path segment size. The multiple processor device then interprets the stored decoded data segment with respect to a corresponding one of the plurality of virtual channels to determine a destination of the stored decoded data segment. The multiple processor device then stores the decoded data segment as part of reassembled data.
摘要翻译：多处理器设备将数据流存储为多个数据段，其包括来自多个虚拟通道中的至少一个的多路复用数据片段。构成数据流的数据段对应于来自虚拟通道的复用数据片段。多处理器设备然后根据多个传输协议之一对至少一个数据段进行解码，以产生解码的数据段。然后，多处理器设备存储解码的数据段，以根据数据路径段大小进行对准。然后，多处理器设备相对于多个虚拟通道中的相应一个解码存储的解码数据段，以确定存储的解码数据段的目的地。然后，多处理器设备将解码的数据段存储为重新组装的数据的一部分。

3. 发明申请

US20070271402A1 Partially Populated, Hierarchical Crossbar 有权
标题翻译：部分填充，分层交叉
公开(公告)号：US20070271402A1
公开(公告)日：2007-11-22
申请号：US11832841
申请日：2007-08-02
申请人： Sridhar Subramanian , James Keller , George Yiu , Ruchi Wadhawan
发明人： Sridhar Subramanian , James Keller , George Yiu , Ruchi Wadhawan
IPC分类号： G06F13/00
CPC分类号： G06F13/364 , G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality of selection circuits) to form communication paths between the agents, and a first segment is included in a first communication path from the first agent to the second agent, and is also included in a second communication path from the third agent to the fourth agent. In another embodiment, each segment is driven by a selection circuit. At least one selection circuit has at least one segment and an output from at least one agent as inputs. In yet another embodiment, an arbiter is configured to determine a communication path on the interconnect for each requesting agent to the destination agent over the segments. The arbiter is configured to arbitrate among a subset of requests for which each segment in the corresponding communication path is available.
摘要翻译：在各种实施例中，装置包括多个代理和互连。在一个实施方案中，多种试剂包括第一至第四试剂。互连包括可切换的多个段（例如，使用多个选择电路）以形成代理之间的通信路径，并且第一段包括在从第一代理到第二代理的第一通信路径中，并且还包括在从第三代理到第四代理的第二通信路径中。在另一实施例中，每个段由选择电路驱动。至少一个选择电路具有至少一个段和来自至少一个代理的输出作为输入。在另一个实施例中，仲裁器被配置为确定每个请求代理在该互连上的通信路径到该段上的目的地代理。仲裁器被配置为在对应的通信路径中的每个段可用的请求的子集之间进行仲裁。

4. 发明授权

US08962808B2 EGFR-related polypeptides and methods of use 有权
标题翻译： EGFR相关多肽和使用方法
公开(公告)号：US08962808B2
公开(公告)日：2015-02-24
申请号：US13696291
申请日：2011-05-05
申请人： Edward L. Chan , James Keller
发明人： Edward L. Chan , James Keller
IPC分类号： C07K16/00 , C12Q1/68 , C07K14/71 , G01N33/574 , C07K16/40 , C12N9/12 , G01N33/74
CPC分类号： C12Q1/6886 , C07K14/71 , C07K16/40 , C07K2319/00 , C07K2319/23 , C07K2319/42 , C07K2319/43 , C07K2319/60 , C12N9/12 , G01N33/57407 , G01N33/74 , G01N2333/71 , G01N2800/56
摘要： Described herein are truncated EGF receptor polypeptides, nucleic acids encoding them, and methods of using them to help select a method of treatment for an EGFR-related cancer, to predict clinical outcome, and to detect micrometastases or minimal residual disease. High EGFR expression and phosphorylated EGFR predicts poor survival in head and neck cancer patients, but does not correlate with advanced stage disease. In our studies, we determined that clinical biological correlates are likely to be more accurate when different aspects of EGFR are evaluated in combination. We analyzed EGFR phosphorylation, expression and mutations in 60 primary head and neck tumors. We not only found that head and neck tumors with either truncated or activated EGFR tend to have higher tumor and nodal stage, but also discovered three EGFR truncations.
摘要翻译：本文描述的是截短的EGF受体多肽，编码它们的核酸，以及使用它们帮助选择EGFR相关癌症的治疗方法，预测临床结果以及检测微转移或微小残留疾病的方法。高EGFR表达和磷酸化EGFR预测头颈癌患者的生存率差，但与晚期阶段疾病无关。在我们的研究中，我们确定临床生物相关性可以更准确地评估EGFR的不同方面。我们分析了60例原发性头颈部肿瘤中的EGFR磷酸化，表达和突变。我们不仅发现具有截短或活化的EGFR的头颈部肿瘤倾向于具有较高的肿瘤和淋巴结阶段，而且还发现三个EGFR截短。

5. 发明申请

US20120226542A1 PROVIDING COUPONS VIA A MOBILE DEVICE 审中-公开
标题翻译：通过移动设备提供优惠
公开(公告)号：US20120226542A1
公开(公告)日：2012-09-06
申请号：US13356566
申请日：2012-01-23
申请人： Nicholas Blosser , Greg Keene , James Keller , Raven Zachary , Jennifer Adams
发明人： Nicholas Blosser , Greg Keene , James Keller , Raven Zachary , Jennifer Adams
IPC分类号： G06Q30/02
CPC分类号： G06Q30/02
摘要： A facility for distributing electronic coupons is described. The facility presents to a user indications of each of at least one coupon pack. Each coupon pack comprises a plurality of independently-redeemable electronic coupons. The facility receives user input selecting an indicated coupon pack, and uses payment information associated with the user to collect a price indicated for the selected coupon pack. The facility then makes the selected coupon pack available for use by the user such that the user may redeem any of the electronic coupons of the selected coupon pack.
摘要翻译：描述了分发电子券的设施。该设施向用户呈现每个至少一个优惠券包的指示。每个优惠券包包括多个独立可兑换的电子优惠券。该设施接收用户输入选择所指示的优惠券包，并且使用与用户相关联的支付信息来收集针对所选优惠券组指示的价格。然后，该设施使所选择的优惠券包可供用户使用，使得用户可以兑换所选择的优惠券包的任何电子优惠券。

6. 发明申请

US20060180528A1 Waste water recovery system 有权
标题翻译：废水回收系统
公开(公告)号：US20060180528A1
公开(公告)日：2006-08-17
申请号：US11060112
申请日：2005-02-17
申请人： James Keller
发明人： James Keller
IPC分类号： B01D35/16
CPC分类号： B01D35/12 , B01D29/114 , B01D29/66 , Y10S15/02
摘要： A waste water recovery system to filter and recirculate waste water to a wash system including a fluid recovery line, a fluid supply line and a fluid backwash line comprising a filter assembly including a water filtering section to receive waste water from the wash system and to recirculate filtered water to the wash system and a filter backwash section to selectively clean the water filtering section when a system condition exists, and a fluid control including a plurality of valve assemblies operatively coupled between the wash system, the water filtering section and the filter backwash section to selectively control the circulation of water through the water filtering section to recirculate the recovery water to the wash system and to periodically clean the water filtering section.
摘要翻译：一种用于将废水过滤并再循环到洗涤系统的废水回收系统，所述洗涤系统包括流体回收管线，流体供应管线和流体反洗管线，其包括过滤器组件，所述过滤器组件包括用于从洗涤系统接收废水并再循环过滤水到洗涤系统和过滤器反冲洗部分，以在系统状态存在时选择性地清洁水过滤部分，以及包括多个阀组件的流体控制器，其可操作地联接在洗涤系统，水过滤部分和过滤器反冲洗部分以选择性地控制水通过水过滤部分的循环，以将回收水再循环到洗涤系统并周期性地清洁水过滤部分。

7. 发明申请

US20050232287A1 High speed bus system that incorporates uni-directional point-to-point buses 失效
标题翻译：采用单向点对点总线的高速总线系统
公开(公告)号：US20050232287A1
公开(公告)日：2005-10-20
申请号：US11152213
申请日：2005-06-14
申请人： Raj Ramanujan , James Keller , William Samaras , John De Rosa , Robert Stewart
发明人： Raj Ramanujan , James Keller , William Samaras , John De Rosa , Robert Stewart
IPC分类号： G06F15/167 , G06F15/173 , H04L12/28 , H04L12/403
CPC分类号： H04L12/403 , G06F15/167 , G06F15/173 , H04L12/4625
摘要： An apparatus comprises a plurality of ports wherein each port is adapted to couple to a device. At least one port connects by way of first and second unidirectional, point-to-point communication links with a device. The first unidirectional, point-to-point communication link transfers data from the device to the central logic unit and the second unidirectional, point-to-point communication link transfers data from the central logic unit to the device.
摘要翻译：一种装置包括多个端口，其中每个端口适于耦合到设备。至少一个端口通过与设备的第一和第二单向，点对点通信链路连接。第一单向点对点通信链路将数据从设备传送到中央逻辑单元，第二单向点对点通信链路将数据从中央逻辑单元传送到设备。

8. 发明申请

US20070050564A1 Combined buffer for snoop, store merging, load miss, and writeback operations 有权
标题翻译：组合缓冲区，用于侦听，存储合并，加载错误和回写操作
公开(公告)号：US20070050564A1
公开(公告)日：2007-03-01
申请号：US11215604
申请日：2005-08-30
申请人： Ramesh Gunna , Po-Yung Chang , Sridhar Subramanian , James Keller , Tse-Yuh Yeh
发明人： Ramesh Gunna , Po-Yung Chang , Sridhar Subramanian , James Keller , Tse-Yuh Yeh
IPC分类号： G06F13/28
CPC分类号： G06F12/0831
摘要： In one embodiment, an interface unit comprises an address buffer and a control unit coupled to the address buffer. The address buffer is configured to store addresses of processor core requests generated by a processor core and addresses of snoop requests received from an interconnect. The control unit is configured to maintain a plurality of queues, wherein at least a first queue of the plurality of queues is dedicated to snoop requests and at least a second queue of the plurality of queues is dedicated to processor core requests. Responsive to a first snoop request received by the interface unit from the interconnect, the control unit is configured to allocate a first address buffer entry of the address buffer to store the first snoop request and to store a first pointer to the first address buffer entry in the first queue. Responsive to a first processor core request received by the interface unit from the processor core, the control unit is configured to allocate a second address buffer entry of the address buffer to store the first processor core request and to store a second pointer to the second address buffer entry in the second queue.
摘要翻译：在一个实施例中，接口单元包括地址缓冲器和耦合到地址缓冲器的控制单元。地址缓冲器被配置为存储由处理器核心产生的处理器核心请求的地址和从互连接收的窥探请求的地址。所述控制单元被配置为维护多个队列，其中所述多个队列中的至少第一队列专用于窥探请求，并且所述多个队列中的至少第二队列专用于处理器核心请求。响应于接口单元从互连接收到的第一窥探请求，控制单元被配置为分配地址缓冲器的第一地址缓冲器条目以存储第一窥探请求，并且将第一指针存储到第一地址缓冲器条目中第一个队列。响应于接口单元从处理器核心接收到的第一处理器核心请求，控制单元被配置为分配地址缓冲器的第二地址缓冲器条目以存储第一处理器核心请求并将第二指针存储到第二地址第二个队列中的缓冲区条目。

9. 发明申请

US20070038791A1 Non-blocking address switch with shallow per agent queues 有权
标题翻译：非阻塞地址切换，每个代理队列较浅
公开(公告)号：US20070038791A1
公开(公告)日：2007-02-15
申请号：US11201581
申请日：2005-08-11
申请人： Sridhar Subramanian , James Keller , Ruchi Wadhawan , George Yiu , Ramesh Gunna
发明人： Sridhar Subramanian , James Keller , Ruchi Wadhawan , George Yiu , Ramesh Gunna
IPC分类号： G06F13/36
CPC分类号： G06F13/362 , G06F13/4022
摘要： In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.
摘要翻译：在一个实施例中，开关被配置为耦合到互连。开关包括多个存储位置和耦合到多个存储位置的仲裁器控制电路。多个存储位置被配置为存储由多个代理发送的多个请求。仲裁器控制电路被配置为在存储在多个存储位置中的多个请求之间进行仲裁。所选择的请求是仲裁的赢家，并且交换机被配置为将所选择的请求从多个存储位置之一发送到互连上。在另一个实施例中，系统包括多个代理，互连和耦合到多个代理和互连的开关。在另一个实施例中，预期了一种方法。

10. 发明申请

US20070011368A1 Digital phase relationship lock loop 有权
标题翻译：数字相位锁定环路
公开(公告)号：US20070011368A1
公开(公告)日：2007-01-11
申请号：US11176520
申请日：2005-07-07
申请人： James Wang , Zongjian Chen , James Keller
发明人： James Wang , Zongjian Chen , James Keller
IPC分类号： G06F5/00
CPC分类号： G06F5/14
摘要： In one embodiment, an apparatus comprises a first clocked storage device operable in a first clock domain corresponding to a first clock signal. The first clocked storage device has an input coupled to receive one or more bits transmitted on the input from a second clock domain corresponding to a second clock signal. The apparatus further comprises control circuitry configured to ensure that a change in a value of the one or more bits transmitted on the input meets setup and hold time requirements of the first clocked storage device. The control circuitry is responsive to a sample history of one of the first clock signal or the second clock signal to detect a phase relationship between the first clock signal and the second clock signal on each clock cycle to ensure the change meets the setup and hold time requirements.
摘要翻译：在一个实施例中，一种装置包括可在对应于第一时钟信号的第一时钟域中操作的第一时钟存储装置。第一时钟存储设备具有耦合以接收从对应于第二时钟信号的第二时钟域在输入上发送的一个或多个位的输入。该装置还包括控制电路，其被配置为确保在输入上传输的一个或多个比特的值的变化满足第一时钟存储设备的建立和保持时间要求。控制电路响应于第一时钟信号或第二时钟信号之一的采样历史，以在每个时钟周期上检测第一时钟信号和第二时钟信号之间的相位关系，以确保改变满足建立和保持时间要求。

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