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1. 发明授权

US07719098B2 Stacked modules and method 有权
标题翻译：堆叠模块和方法
公开(公告)号：US07719098B2
公开(公告)日：2010-05-18
申请号：US11873351
申请日：2007-10-16
申请人： James Douglas Wehrly, Jr.
发明人： James Douglas Wehrly, Jr.
IPC分类号： H01L23/538
CPC分类号： H01L25/105 , H01L21/4871 , H01L23/3114 , H01L23/49833 , H01L23/49838 , H01L23/4985 , H01L23/5385 , H01L23/5387 , H01L24/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/00011 , H01L2924/00014 , H01L2924/14 , H01L2924/3511 , Y10T29/49169 , Y10T29/53209 , Y10T29/5327 , H01L2924/00012 , H01L2224/0401
摘要： The present invention stacks integrated circuits into modules that conserve board surface area. In a precursor assembly devised as a component for a stacked circuit module in accordance with a preferred embodiment of the present invention, one or more stiffeners are disposed at least partially between a flex circuit and an integrated circuit. In a two-high stacked circuit module devised in accordance with a preferred embodiment of the present invention, an integrated circuit is stacked above a precursor assembly. The two integrated circuits are connected with the flex circuit of the precursor assembly. The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules.
摘要翻译：本发明将集成电路堆叠成节省电路板表面积的模块。在根据本发明的优选实施例设计为用于堆叠电路模块的部件的前驱体组件中，一个或多个加强件至少部分地设置在柔性电路和集成电路之间。在根据本发明的优选实施例设计的两层叠层电路模块中，集成电路堆叠在前体组件的上方。两个集成电路与前体组件的柔性电路连接。本发明可以有益于模块中集成电路的多种配置和组合。

2. 发明授权

US07542304B2 Memory expansion and integrated circuit stacking system and method 有权
标题翻译：内存扩展和集成电路堆叠系统及方法
公开(公告)号：US07542304B2
公开(公告)日：2009-06-02
申请号：US10804452
申请日：2004-03-19
申请人： Russell Rapport , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr. , Jeff Buchle
发明人： Russell Rapport , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr. , Jeff Buchle
IPC分类号： H01R9/00
CPC分类号： H01L25/105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2225/107 , H01L2924/3011 , H01L2924/00012
摘要： The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.
摘要翻译：本发明将集成电路（IC）堆叠成节省PWB或其他板表面积的模块。在另一方面，本发明提供了一种较低电容存储器扩展寻址系统和方法，并且优选地具有本文提供的CSP堆叠模块。在根据本发明的优选实施例中，形式标准提供了一种物理形式，其允许在广泛的CSP封装系列中发现的许多变化的封装尺寸在使用标准连接柔性电路设计时被有利地使用。在优选实施例中，将设计形式标准，以便传热材料例如铜，以改善热性能。在存储器寻址系统的优选实施例中，高速交换系统选择与堆叠模块的每个级别相关联的数据线，以减少对存储器访问中的数据信号的负载影响。

3. 发明授权

US07443023B2 High capacity thin module system 有权
标题翻译：大容量薄模块系统
公开(公告)号：US07443023B2
公开(公告)日：2008-10-28
申请号：US11231418
申请日：2005-09-21
申请人： James Douglas Wehrly, Jr. , James Wilder , Paul Goodwin , Mark Wolfe
发明人： James Douglas Wehrly, Jr. , James Wilder , Paul Goodwin , Mark Wolfe
IPC分类号： H01L23/34 , H01L21/00 , H05K7/20
CPC分类号： H05K1/189 , H05K1/0203 , H05K1/11 , H05K1/181 , H05K3/0061 , H05K2201/056 , H05K2201/09445 , H05K2201/10159 , H05K2201/1056 , H05K2201/10734 , H05K2203/1572
摘要： Flexible circuitry is populated with integrated circuitry disposed along one or both of its major sides. Contacts distributed along the flexible circuitry provide connection between the module and an application environment. The circuit-populated flexible circuitry is disposed about an edge of a rigid substrate thus placing the integrated circuitry on one or both sides of the substrate with one or two layers of integrated circuitry on one or both sides of the substrate. The substrate form is preferably devised from thermally conductive materials and includes a high thermal conductivity core or area that is disposed proximal to higher thermal energy devices such as an AMB when the flex circuit is brought about the substrate. Other variations include thermally-conductive clips that grasp respective ICs on opposite sides of the module to further shunt heat from the ICs. Preferred extensions from the substrate body or substrate core encourage reduced thermal variations amongst the integrated circuits of the module.
摘要翻译：灵活的电路填充有沿其主要侧面或其两侧设置的集成电路。沿柔性电路分布的触点提供模块与应用环境之间的连接。电路填充的柔性电路围绕刚性衬底的边缘设置，从而将集成电路放置在衬底的一侧或两侧，在衬底的一侧或两侧上具有一层或两层集成电路。衬底形式优选地由导热材料设计，并且当柔性电路绕在衬底上时，包括设置在较高热能器件（例如AMB）附近的高导热性芯或区域。其他变型包括将模块的相对侧上的相应IC夹持的导热夹子，以进一步从IC分流热量。来自衬底主体或衬底芯的优选延伸部件促进模块集成电路之间的热变化减小。

4. 发明授权

US07304382B2 Managed memory component 有权
公开(公告)号：US07304382B2
公开(公告)日：2007-12-04
申请号：US11436957
申请日：2006-05-18
申请人： James Douglas Wehrly, Jr. , Ron Orris , Leland Szewerenko , Tim Roy , Julian Partridge , David L. Roper
发明人： James Douglas Wehrly, Jr. , Ron Orris , Leland Szewerenko , Tim Roy , Julian Partridge , David L. Roper
IPC分类号： H01L23/34
CPC分类号： H01L23/13 , H01L23/5385 , H01L23/5387 , H01L25/18 , H01L2224/49175 , H01L2924/15311 , H05K1/147 , H05K1/182 , H05K1/189 , H05K3/326 , H05K2201/056 , H05K2201/091 , H05K2201/10515 , H05K2201/10689
摘要： The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry to reduce footprint for the combination. A leaded IC package is disposed along the obverse side of a flex circuit. In a preferred embodiment, leads of the leaded IC package are configured to allow the lower surface of the body of the leaded IC package to contact the surface of the flex circuitry either directly or indirectly through an adhesive. A semiconductor die is connected to the reverse side of the flex circuit. In one embodiment, the semiconductor die is disposed on the reverse side of the flex while, in an alternative embodiment, the semiconductor die is disposed into a window in the flex circuit to rest directly or indirectly upon the body of the leaded IC package. Module contacts are provided in a variety of configurations. In a preferred embodiment, the leaded IC package is a flash memory and the semiconductor die is a controller.

5. 发明授权

US07202555B2 Pitch change and chip scale stacking system and method 有权
标题翻译：间距变换和芯片级堆叠系统及方法
公开(公告)号：US07202555B2
公开(公告)日：2007-04-10
申请号：US11074026
申请日：2005-03-08
申请人： David L. Roper , James W. Cady , James Wilder , James Douglas Wehrly, Jr. , Jeff Buchle , Julian Dowden
发明人： David L. Roper , James W. Cady , James Wilder , James Douglas Wehrly, Jr. , Jeff Buchle , Julian Dowden
IPC分类号： H01L23/02
CPC分类号： H01L23/49816 , H01L23/3114 , H01L23/49827 , H01L23/4985 , H01L23/5386 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16237 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/0002 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/058 , H05K2201/10734 , H01L2924/0001
摘要： The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower integrated circuit of the module. The flex circuit pair connects the upper and lower integrated circuits and provides a thermal and electrical path connection path between the module and its application environment. The module has a bailout pattern with a different pitch and/or supplemental module contacts devised to allow combined signaling to the integrated circuits through contacts having a desired ballout footprint. The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules provided for high-density memories or high capacity computing.
摘要翻译：本发明将集成电路堆叠成节省电路板表面积的模块。在根据本发明的优选实施例设计的两高堆叠或模块中，堆叠一对集成电路，一个集成电路在另一个之上。两个集成电路与一对柔性电路结构连接。一对柔性电路结构中的每一个部分地缠绕在模块的下部集成电路的相应的相对侧边缘上。柔性电路对连接上下集成电路，并在模块与其应用环境之间提供热和电路连接路径。该模块具有一个具有不同间距和/或补充模块触点的救援模式，用于允许通过具有期望的展开足迹的触点对集成电路的组合信令。本发明可以有利于提供用于高密度存储器或高容量计算的模块中的集成电路的多种配置和组合。

6. 发明授权

US07033861B1 Stacked module systems and method 有权
公开(公告)号：US07033861B1
公开(公告)日：2006-04-25
申请号：US11131812
申请日：2005-05-18
申请人： Julian Partridge , James Douglas Wehrly, Jr. , David Roper
发明人： Julian Partridge , James Douglas Wehrly, Jr. , David Roper
IPC分类号： H01L21/44
CPC分类号： H05K3/3436 , H01L23/36 , H01L23/49816 , H01L23/4985 , H01L25/105 , H01L25/50 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73253 , H01L2225/1041 , H01L2225/1058 , H01L2225/107 , H01L2924/00011 , H01L2924/00014 , H05K1/189 , H05K3/305 , H05K2203/0278 , Y02P70/613 , H01L2224/0401
摘要： A combination composed from a form standard and a CSP is attached to flex circuitry. Solder paste is applied to first selected locations on the flex circuitry and adhesive is applied to second selected locations on the flex circuitry. The flex circuitry and the combination of the form standard and CSP are brought into proximity with each other. During solder reflow operation, a force is applied that tends to bring the combination and flex circuitry closer together. As the heat of solder reflow melts the contacts of the CSP, the combination collapses toward the flex circuitry displacing the adhesive as the solder paste and contacts merge into solder joints. In a preferred embodiment, the form standard will be devised of heat transference material, a metal, for example, such as copper would be preferred, to improve thermal performance. In other embodiments, the methods of the invention may be used to attach a CSP without a form standard to flex circuitry.

7. 发明授权

US06893899B2 Contact member stacking system and method 有权
标题翻译：接触件堆垛系统及方法
公开(公告)号：US06893899B2
公开(公告)日：2005-05-17
申请号：US10814531
申请日：2004-03-31
申请人： James Douglas Wehrly, Jr.
发明人： James Douglas Wehrly, Jr.
IPC分类号： H01L25/10 , H01L21/44 , H01L21/48 , H01L21/50 , H01L23/02
CPC分类号： H01L25/105 , H01L2225/1005 , H01L2225/1029 , H01L2225/107 , H01L2924/0002 , H01L2924/00
摘要： A system and method for selectively stacking and interconnecting individual integrated circuit devices to create a high-density integrated circuit module. In a preferred embodiment, conventional thin small outline packaged (TSOP) memory circuits are vertically stacked one above the other. The constituent IC elements act in concert to provide an assembly of memory capacity approximately equal to the sum of the capacities of the ICs that constitute the assembly. The IC elements of the stack are electrically connected through individual contact members that connect corresponding leads of IC elements positioned adjacently in the stack. In a preferred embodiment, the contact members are composed of lead frame material. Methods for creating stacked integrated circuit modules are provided that provide reasonable cost, mass production techniques to produce modules. In a preferred method, a carrier frame of lead frame material is configured to present an opening into which opening project plural lead-like contact members that correspond to the leads of an IC element. The contact members contact the leads of the lower IC element of the stack while the leads of the upper IC of the assembly contact the upper surfaces of the contact members. The stack is assembled using typical surface mount equipment and, after assembly, the carrier portion of the frame is removed to leave the plurality of contact members in place between selected leads.
摘要翻译：一种用于选择性堆叠和互连各个集成电路器件以创建高密度集成电路模块的系统和方法。在优选实施例中，传统的薄小外形封装（TSOP）存储器电路一个在另一个之上垂直堆叠。组成的IC元件一致地提供大约等于构成组件的IC的容量之和的存储器容量的组合。堆叠的IC元件通过单独的接触构件电连接，该接触构件连接相邻于IC堆叠的IC元件的相应引线。在优选实施例中，接触构件由引线框架材料构成。提供了制造堆叠集成电路模块的方法，其提供合理的成本，批量生产技术来生产模块。在优选的方法中，引线框架材料的载体框架构造成具有开口，该开口突出了与IC元件的引线相对应的多个引线状接触构件。接触构件接触堆叠的下部IC元件的引线，而组件的上部IC的引线接触接触构件的上表面。堆叠使用典型的表面贴装设备组装，并且在组装之后，移除框架的托架部分以使多个接触构件在选定的引线之间就位。

8. 发明授权

US07759791B2 High density IC module 有权
标题翻译：高密度IC模块
公开(公告)号：US07759791B2
公开(公告)日：2010-07-20
申请号：US11738330
申请日：2007-04-20
申请人： Julian Partridge , Leland Szewerenko , James Douglas Wehrly, Jr.
发明人： Julian Partridge , Leland Szewerenko , James Douglas Wehrly, Jr.
IPC分类号： H01L23/34
CPC分类号： H01L25/0657 , H01L23/5387 , H01L24/81 , H01L24/90 , H01L2224/81203 , H01L2224/81205 , H01L2224/81801 , H01L2224/90 , H01L2225/06517 , H01L2225/0652 , H01L2225/06572 , H01L2225/06582 , H01L2225/06589 , H01L2924/01327 , H01L2924/09701 , H01L2924/14 , H01L2924/00
摘要： A system and method for assembling dual-die integrated circuit packages using thermocompression bonding or thermosonic bonding to bond a second die to a substrate opposite a first die bonded to the substrate. The second die is bonded using heat conducted through the first die to the substrate, and optionally through an underfill material. The first and second die are connected such that bumps are connected to common bonding pads on the substrate. Bumps on one of the die extend through openings in the substrate to connect to the common bonding pads. The bonding pads are within the perimeter of the first die.
摘要翻译：一种用于使用热压接或热超声结合来组装双模集成电路封装的系统和方法，用于将第二裸片结合到与衬底相连的第一裸片相对的衬底上。第二模具使用通过第一模具传导的热量粘合到基底上，并且任选地通过底部填充材料粘合。连接第一和第二裸片，使得凸块连接到基板上的公共接合焊盘。其中一个模具上的凸起延伸穿过基板中的开口以连接到公共接合焊盘。接合焊盘位于第一管芯的周边内。

9. 发明授权

US07737549B2 Circuit module with thermal casing systems 失效
标题翻译：具有热套管系统的电路模块
公开(公告)号：US07737549B2
公开(公告)日：2010-06-15
申请号：US12263060
申请日：2008-10-31
申请人： James Douglas Wehrly, Jr. , James Wilder , Mark Wolfe , Paul Goodwin
发明人： James Douglas Wehrly, Jr. , James Wilder , Mark Wolfe , Paul Goodwin
IPC分类号： H01L23/34 , H05K7/20 , H01L21/00
CPC分类号： H05K1/189 , H05K1/0203 , H05K1/11 , H05K1/181 , H05K3/0061 , H05K2201/056 , H05K2201/09445 , H05K2201/10159 , H05K2201/1056 , H05K2201/10734 , H05K2203/1572
摘要： Flexible circuitry is populated with integrated circuitry (ICs), and contacts are distributed along the flexible circuitry to provide connection to an application environment. The flexible circuitry is disposed about a rigid substrate, placing the ICs on one or both sides of the substrate with one or more layers of integrated circuitry on one or both sides of the substrate. The substrate is preferably devised from thermally-conductive materials and one or more thermal spreaders are in thermal contact with at least some of the ICs. Optionally, as an additional thermal management feature, the module may include a high thermal conductivity thermal sink or area that is disposed proximal to higher thermal energy IC devices. In preferred embodiments, extensions from the substrate body or substrate core encourage reduced thermal variations amongst the ICs of the module while providing an enlarged surface for shedding thermal energy from the module.
摘要翻译：灵活的电路采用集成电路（IC），并且触点沿柔性电路分布，以提供与应用环境的连接。柔性电路围绕刚性衬底设置，将IC放置在衬底的一侧或两侧上，在衬底的一侧或两侧上具有一层或多层集成电路。衬底优选地由导热材料设计，并且一个或多个热扩散器与至少一些IC热接触。可选地，作为附加的热管理特征，模块可以包括设置在较高热能IC器件附近的高导热性散热器或区域。在优选实施例中，来自衬底主体或衬底芯的延伸部促进模块的IC之间的热变化减小，同时提供用于从模块中排出热能的放大表面。

10. 发明授权

US07626259B2 Heat sink for a high capacity thin module system 有权
标题翻译：散热器用于高容量薄模块系统
公开(公告)号：US07626259B2
公开(公告)日：2009-12-01
申请号：US12258189
申请日：2008-10-24
申请人： James Douglas Wehrly, Jr. , James Wilder , Paul Goodwin , Mark Wolfe
发明人： James Douglas Wehrly, Jr. , James Wilder , Paul Goodwin , Mark Wolfe
IPC分类号： H01L23/34 , H01L21/00 , H05K7/20
CPC分类号： H05K1/189 , H05K1/0203 , H05K1/11 , H05K1/181 , H05K3/0061 , H05K2201/056 , H05K2201/09445 , H05K2201/10159 , H05K2201/1056 , H05K2201/10734 , H05K2203/1572
摘要： Flexible circuitry is populated with integrated circuitry disposed along one or both of its major sides. Contacts distributed along the flexible circuitry provide connection between the module and an application environment. The circuit-populated flexible circuitry is disposed about an edge of a rigid substrate thus placing the integrated circuitry on one or both sides of the substrate with one or two layers of integrated circuitry on one or both sides of the substrate. The substrate form is preferably devised from thermally conductive materials and includes a high thermal conductivity core or area that is disposed proximal to higher thermal energy devices such as an AMB when the flex circuit is brought about the substrate. Other variations include thermally-conductive clips that grasp respective ICs on opposite sides of the module to further shunt heat from the ICs. Preferred extensions from the substrate body or substrate core encourage reduced thermal variations amongst the integrated circuits of the module.
摘要翻译：灵活的电路填充有沿其主要侧面或其两侧设置的集成电路。沿柔性电路分布的触点提供模块与应用环境之间的连接。电路填充的柔性电路围绕刚性衬底的边缘设置，从而将集成电路放置在衬底的一侧或两侧，在衬底的一侧或两侧上具有一层或两层集成电路。衬底形式优选地由导热材料设计，并且当柔性电路绕在衬底上时，包括设置在较高热能器件（例如AMB）附近的高导热性芯或区域。其他变型包括将模块的相对侧上的相应IC夹持的导热夹子，以进一步从IC分流热量。来自衬底主体或衬底芯的优选延伸部件促进模块集成电路之间的热变化减小。

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