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1. 发明申请

WO2007056893A1 LATENCY HIDING OF TRACES USING BLOCK COLORING 审中-公开
标题翻译：使用块颜色隐藏跟踪的隐藏
公开(公告)号：WO2007056893A1
公开(公告)日：2007-05-24
申请号：PCT/CN2005/001960
申请日：2005-11-18
申请人： INTEL CORPORATION , GUO, Xiaofeng , DAI, Jinquan , LI, Long , LV, Zhiyuan
发明人： GUO, Xiaofeng , DAI, Jinquan , LI, Long , LV, Zhiyuan
IPC分类号： G06F9/38
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3838 , G06F9/3851
摘要： An embodiment of the present invention is a technique to hide latency in program traces. Blocks of instructions between start and end of a critical section are associated with color information. The blocks correspond to a program trace and containing a wait instruction. The wait instruction is sunk down the blocks globally to the end of the critical section using the color information and a dependence constraint on the wait instruction.
摘要翻译：本发明的一个实施例是一种在程序轨迹中隐藏延迟的技术。关键部分的开始和结束之间的指令块与颜色信息相关联。这些块对应于程序跟踪并包含等待指令。等待指令使用颜色信息和等待指令的依赖约束将全局块下降到关键部分的末尾。

2. 发明申请

WO2007073611A1 METHOD AND APPARATUS FOR ORDERING CODE BASED ON CRITICAL SECTIONS 审中-公开
标题翻译：基于关键部分订购代码的方法和装置
公开(公告)号：WO2007073611A1
公开(公告)日：2007-07-05
申请号：PCT/CN2005/002307
申请日：2005-12-24
申请人： INTEL CORPORATION , LI, Long , DAI, Jinquan , GUO, Xiaofeng
发明人： LI, Long , DAI, Jinquan , GUO, Xiaofeng
IPC分类号： G06F9/45
CPC分类号： G06F8/445
摘要： A method of compiling code includes ordering instructions that protect and release critical sections in the code to improve parallel execution of the code according to an intrinsic order of the critical sections. According to one embodiment, the intrinsic order of the critical sections in the code is determined from data dependence and control dependence of instructions in the critical sections, and additional dependencies are generated to enforce the intrinsic order of the critical sections. Other embodiments are described and claimed.
摘要翻译：一种编译代码的方法包括排序指令，用于保护和释放代码中的关键部分，以根据关键部分的内在顺序改进代码的并行执行。根据一个实施例，代码中的关键部分的固有顺序是根据关键部分中的指令的数据依赖性和控制依赖性来确定的，并且生成额外的依赖性以强制关键部分的内在顺序。描述和要求保护其他实施例。

3. 发明申请

WO2007085121A1 SCHEDULING MULTITHREADED PROGRAMMING INSTRUCTIONS BASED ON DEPENDENCY GRAPH 审中-公开
标题翻译：根据附录图表调度多项式编程指令
公开(公告)号：WO2007085121A1
公开(公告)日：2007-08-02
申请号：PCT/CN2006/000162
申请日：2006-01-26
申请人： INTEL CORPORATION , GUO, Xiaofeng , DAI, Jinquan , LI, Long
发明人： GUO, Xiaofeng , DAI, Jinquan , LI, Long
IPC分类号： G06F9/00
CPC分类号： G06F8/445
摘要： A computer implemented method for scheduling multithreaded programming instructions based on the dependency graph wherein the dependency graph organizes the programming instruction logically based on blocks, nodes, and super blocks and wherein the programming instructions could be executed outside of a critical section may be executed outside of the critical section by inserting dependency relationship in the dependency graph.
摘要翻译：一种基于依赖图来调度多线程编程指令的计算机实现方法，其中所述依赖图基于块，节点和超级块逻辑地组织所述编程指令，并且其中所述编程指令可以在关键部分之外执行，关键部分通过在依赖关系图中插入依赖关系。

4. 发明申请

WO2007065308A1 SPECULATIVE CODE MOTION FOR MEMORY LATENCY HIDING 审中-公开
标题翻译：用于存储器隐藏隐藏的调制代码运动
公开(公告)号：WO2007065308A1
公开(公告)日：2007-06-14
申请号：PCT/CN2005/002150
申请日：2005-12-10
申请人： INTEL CORPORATION , LI, Long , DAI, Jinquan , LV, Zhiyuan
发明人： LI, Long , DAI, Jinquan , LV, Zhiyuan
IPC分类号： G06F9/45
CPC分类号： G06F9/30079 , G06F8/41 , G06F9/3004 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： Various embodiments that may be used in performing speculative code motion for memory latency hiding are disclosed. One embodiment comprises extracting an asynchronous signal from a memory access instruction in a program to represent a latency of the memory access instruction, and generating a wait instruction to wait the asynchronous signal.
摘要翻译：公开了可用于执行用于存储器延迟隐藏的推测性代码运动的各种实施例。一个实施例包括从程序中的存储器访问指令中提取异步信号以表示存储器访问指令的等待时间，以及生成等待异步信号的等待指令。

5. 发明申请

WO2007000081A1 METHODS, APPARATUS, AND SYSTEMS FOR CACHING 审中-公开
标题翻译：方法，设备和系统进行缓存
公开(公告)号：WO2007000081A1
公开(公告)日：2007-01-04
申请号：PCT/CN2005/000945
申请日：2005-06-29
申请人： INTEL CORPORATION , DAI, Jinquan , LI, Long
发明人： DAI, Jinquan , LI, Long
IPC分类号： G06F13/00
CPC分类号： G06F9/52 , G06F9/522 , G06F12/0837 , G06F12/0842
摘要： Methods, apparatus, and systems are provided for caching. A caching process is automatically modified in response to update eligibility and an interference relation for a plurality of threads. Data is read into a cache, and a reference to the data is provided to a plurality of threads. An initial thread receives a signal from a last thread once the last thread has the reference to the data. The initial thread, in response to the signal, modifies the data and updates changes to the data within the cache and then sends another signal to a next thread, indicating that the next thread may now perform a volatile operation on the data within the cache.
摘要翻译：为缓存提供了方法，设备和系统。响应于更新资格和多个线程的干扰关系，自动修改缓存过程。将数据读入高速缓存，并将数据的引用提供给多个线程。一旦最后一个线程具有对数据的引用，初始线程将接收来自最后一个线程的信号。初始线程响应于该信号，修改数据并更新缓存内的数据变化，然后向另一个线程发送另一个信号，指示下一个线程现在可以对缓存中的数据执行易失性操作。

6. 发明申请

WO2006074576A1 METHOD AND APPARATUS FOR GENERATING EXECUTION EQUIVALENCE INFORMATION 审中-公开
标题翻译：用于生成执行等效信息的方法和装置
公开(公告)号：WO2006074576A1
公开(公告)日：2006-07-20
申请号：PCT/CN2005/000062
申请日：2005-01-14
申请人： INTEL CORPORATION , DAI, Jinquan , LI, Long , HUANG, Bo
发明人： DAI, Jinquan , LI, Long , HUANG, Bo
IPC分类号： G06F9/45
CPC分类号： G06F8/445
摘要： A method of compiling code includes identifying blocks of code that are execution equivalence pairs. Other embodiments are described and claimed.
摘要翻译：编码的方法包括识别作为执行等价对的代码块。描述和要求保护其他实施例。

7. 发明申请

WO2008019528A1 METHODS AND APPARATUS TO OPTIMIZE COMPUTER INSTRUCTION 审中-公开
标题翻译：优化计算机指令的方法和设备
公开(公告)号：WO2008019528A1
公开(公告)日：2008-02-21
申请号：PCT/CN2006/002006
申请日：2006-08-08
申请人： INTEL CORPORATION , GOU, Xiaofeng , DAI, Jinquan , LI, Long
发明人： GOU, Xiaofeng , DAI, Jinquan , LI, Long
IPC分类号： G06F9/40
CPC分类号： G06F8/445
摘要： Methods and apparatus to optimize computer instructions are disclosed. An example method includes receiving a set of computer instructions, determining a first location of a first computer instruction that indicates the end of a critical section in the set of computer instructions, and modifying the execution order of the set of computer instructions to cause the first computer instruction to be executed earlier than the first location. In an example implementation, the disclosed methods and apparatus may be used to optimize the performance of computer instructions executing on multi-processing computer systems.
摘要翻译：公开了优化计算机指令的方法和装置。示例性方法包括接收一组计算机指令，确定指示计算机指令集中的临界区段的结束的第一计算机指令的第一位置，以及修改该组计算机指令的执行顺序以使第一计算机指令要先于第一个位置执行。在示例实现中，所公开的方法和装置可以用于优化在多处理计算机系统上执行的计算机指令的性能。

8. 发明申请

WO2007085122A1 OPTIMIZING MEMORY ACCESSES FOR NETWORK APPLICATIONS USING INDEXED REGISTER FILES 审中-公开
标题翻译：使用索引寄存器文件优化网络应用程序的存储器访问
公开(公告)号：WO2007085122A1
公开(公告)日：2007-08-02
申请号：PCT/CN2006/000163
申请日：2006-01-26
申请人： INTEL CORPORATION , ZHUANG, Jiangang , DAI, Jinquan , LI, Long
发明人： ZHUANG, Jiangang , DAI, Jinquan , LI, Long
IPC分类号： G06F12/00
CPC分类号： G06F8/4434 , G06F8/441
摘要： A processing device includes an optimizer to migrate objects from an external memory of a network processing device to registers connected to a processor. The optimizer further aligns and eliminates redundant unitialization code of the objects.
摘要翻译：处理设备包括优化器，用于将对象从网络处理设备的外部存储器迁移到连接到处理器的寄存器。优化器进一步对齐并消除对象的冗余单位化代码。

9. 发明申请

WO2005116837A1 AUTOMATIC CACHING GENERATION IN NETWORK APPLICATIONS 审中-公开
标题翻译：网络应用中的自动高速缓存生成
公开(公告)号：WO2005116837A1
公开(公告)日：2005-12-08
申请号：PCT/CN2004/000538
申请日：2004-05-26
申请人： INTEL CORPORATION , DAI, Jinquan , HARRISON, Luddy , LI, Long , HUANG, Bo
发明人： DAI, Jinquan , HARRISON, Luddy , LI, Long , HUANG, Bo
IPC分类号： G06F12/00
CPC分类号： G06F12/0842 , G06F8/4442 , G06F12/0893
摘要： Automatic software controlled caching generations in network applications are described herein. In one embodiment, a candidate representing a plurality of instructions of a plurality of threads that perform one or more external memory accesses is identified, where the external memory accesses have a substantially identical base address. One or more directives and/or instructions are inserted into an instruction stream corresponding to the identified candidate to maintain contents of at least one of a content addressable memory (CAM) and local memory (LM) of a processor, and to modify at least one of the external memory access to access at least one of the CAM and LM of the processor without having to perform the respective external memory access. Other methods and apparatuses are also described.
摘要翻译：本文描述了网络应用中自动软件控制的缓存世代。在一个实施例中，识别表示执行一个或多个外部存储器访问的多个线程的多个指令的候选者，其中外部存储器访问具有基本上相同的基地址。将一个或多个指令和/或指令插入与所识别的候选对应的指令流中，以维持处理器的内容可寻址存储器（CAM）和本地存储器（LM）中的至少一个的内容，并修改至少一个的外部存储器访问以访问处理器的CAM和LM中的至少一个，而不必执行相应的外部存储器访问。还描述了其它方法和装置。

10. 发明申请

WO2005050445A2 AN APPARATUS AND METHOD FOR AN AUTOMATIC THREAD-PARTITION COMPILER 审中-公开
标题翻译：一种用于自动线程分割编译器的装置和方法
公开(公告)号：WO2005050445A2
公开(公告)日：2005-06-02
申请号：PCT/US2004/037161
申请日：2004-11-05
申请人： INTEL CORPORATION , LI, Long , SEED, Cotton , HUANG, Bo , HARRISON, William, III , DAI, Jinquan
发明人： LI, Long , SEED, Cotton , HUANG, Bo , HARRISON, William, III , DAI, Jinquan
IPC分类号： G06F9/45
CPC分类号： G06F8/456 , G06F9/4843
摘要： In some embodiments, a method and apparatus for an automatic thread-partition compiler are described. In one embodiment, the method includes the transformation of a sequential application program into a plurality of application program threads. Once partitioned, the plurality of application program threads are concurrently executed as a respective threads of multi-threaded architecture. Hence, a performance improvement of the parallel multi-threaded architecture is achieved by hiding memory access latency through or by overlapping memory access with computations or with other memory accesses. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，描述了一种用于自动线程分区编译器的方法和装置。在一个实施例中，该方法包括将顺序应用程序转换成多个应用程序线程。一旦分区，多个应用程序线程作为多线程体系结构的相应线程同时执行。因此，并行多线程体系结构的性能改进是通过隐藏存储器访问延迟或通过将存储器访问与计算或其他存储器访问重叠来实现的。描述并要求保护其他实施例。

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