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1. 发明申请

WO2018004953A1 TECHNOLOGIES FOR SCALABLE PACKET RECEPTION AND TRANSMISSION 审中-公开
标题翻译：可扩展分组接收和传输技术
公开(公告)号：WO2018004953A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/035205
申请日：2017-05-31
申请人： INTEL CORPORATION
发明人： BROWNE, John J. , KANTECKI, Tomasz , MACNAMARA, Chris , LAURENT, Pierre , HARTE, Sean
IPC分类号： H04L12/861 , H04L29/08 , G06F13/28
摘要： Technologies for scalable packet reception and transmission include a network device. The network device is to establish a ring that is defined as a circular buffer and includes a plurality of slots to store entries representative of packets. The network device is also to generate and assign receive descriptors to the slots in the ring. Each receive descriptor includes a pointer to a corresponding memory buffer to store packet data. The network device is further to determine whether the NIC has received one or more packets and copy, with direct memory access (DMA) and in response to a determination that the NIC has received one or more packets, packet data of the received one or more packets from the NIC to the memory buffers associated with the receive descriptors assigned to the slots in the ring.
摘要翻译：用于可伸缩分组接收和传输的技术包括网络设备。网络设备将建立被定义为循环缓冲区的环并且包括多个时隙以存储代表分组的条目。网络设备还可以生成接收描述符并将其分配给环中的插槽。每个接收描述符都包含一个指向相应的内存缓冲区的指针以存储分组数据。网络设备进一步确定NIC是否已经接收到一个或多个分组并且利用直接存储器访问（DMA）并且响应于确定NIC已经接收到一个或多个分组来复制所接收的一个或多个分组的数据分组数据将数据包从NIC分配给与分配给环中的插槽的接收描述符关联的内存缓冲区。

2. 发明申请

WO2017218133A1 TECHNOLOGIES FOR COORDINATING ACCESS TO DATA PACKETS IN A MEMORY 审中-公开
标题翻译：用于协调访问存储器中的数据分组的技术
公开(公告)号：WO2017218133A1
公开(公告)日：2017-12-21
申请号：PCT/US2017/033279
申请日：2017-05-18
申请人： INTEL CORPORATION
发明人： BROWNE, John J. , HARTE, Sean , KANTECKI, Tomasz , LAURENT, Pierre , MACNAMARA, Chris
IPC分类号： H04L12/863
CPC分类号： H04L49/9057 , H04L49/102 , H04L49/3063
摘要： Technologies for coordinating access to packets include a network device. The network device is to establish a ring in a memory of the network device. The ring includes a plurality of slots. The network device is also to allocate cores to each of an input stage, an output stage, and a worker stage. The worker stage is to process data in a data packet with an associated worker function. The network device is also to add, with the input stage, an entry to a slot in the ring representative of a data packet received with a network interface controller of the network device, access, with the worker stage, the entry in the ring to process at least a portion of the data packet, and provide, with the output stage, the processed data packet to the network interface controller for transmission.
摘要翻译：
协调数据包访问的技术包括网络设备。网络设备将在网络设备的存储器中建立一个环。该环包括多个槽。网络设备还将内核分配给输入阶段，输出阶段和工作阶段。工作人员阶段是使用相关的辅助功能处理数据包中的数据。网络设备还将与输入阶段一起添加到环中表示与网络设备的网络接口控制器接收的数据分组中的时隙的入口，与工作台一起访问环中的入口到处理数据分组的至少一部分，并且与输出级一起提供处理后的数据分组给网络接口控制器用于传输。

3. 发明公开

EP3462690A1 PACKET SEQUENCE BATCH PROCESSING 有权
公开(公告)号：EP3462690A1
公开(公告)日：2019-04-03
申请号：EP18190103.4
申请日：2018-08-21
申请人： INTEL Corporation
发明人： BROWNE, John J. , MACNAMARA, Christopher , KANTECKI, Tomasz , HERMESH, Barak , HARTE, Sean , CHILIKIN, Andrey , RYAN, Brendan , RICHARDSON, Bruce , O'HANLON, Michael A. , CUNNINGHAM, Andrew
IPC分类号： H04L12/861 , H04L12/931 , H04L12/935
摘要： An apparatus, including: a hardware platform; logic to execute on the hardware platform, the logic configured to: receive a batch including first plurality of packets; identify a common attribute of the batch; perform batch processing on the batch according to the common attribute; generate a hint for the batch, the hint comprising information about the batch to facilitate processing of the batch; and forward the batch to a host platform network interface with the hint.

4. 发明授权

EP3462690B1 PACKET SEQUENCE BATCH PROCESSING 有权
公开(公告)号：EP3462690B1
公开(公告)日：2020-10-28
申请号：EP18190103.4
申请日：2018-08-21
申请人： INTEL Corporation
发明人： BROWNE, John J. , MACNAMARA, Christopher , KANTECKI, Tomasz , HERMESH, Barak , HARTE, Sean , CHILIKIN, Andrey , RYAN, Brendan , RICHARDSON, Bruce , O'HANLON, Michael A. , CUNNINGHAM, Andrew
IPC分类号： H04L12/861 , H04L12/931 , H04L12/935

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