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1. 发明申请

US20110083115A1 ROBUST METHOD FOR INTEGRATION OF BUMP CELLS IN SEMICONDUCTOR DEVICE DESIGN 有权
标题翻译：用于在半导体器件设计中整合保护电池的稳健方法
公开(公告)号：US20110083115A1
公开(公告)日：2011-04-07
申请号：US12575147
申请日：2009-10-07
申请人： Hung-Yi LIU , Chung-Hsing WANG , Agrawal Aditya BINODKUMAR
发明人： Hung-Yi LIU , Chung-Hsing WANG , Agrawal Aditya BINODKUMAR
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A system and method for computer-aided design of semiconductor integrated circuit devices provides for having dummy vias beneath UBM of bump cells to prevent delamination at the bump cell sites during bonding. The dummy vias are inserted into the design and bump cell placement occurs during the floorplanning stage and prior to placement and routing of the active integrated circuit components. In this manner, a sufficiently high via density is achieved and design information on the bump cells including the dummy vias is provided to a computer-aided design, CAD, system along with program instructions for carrying out the indicated sequence of design operations.
摘要翻译：用于半导体集成电路器件的计算机辅助设计的系统和方法提供了在凸块电池的UBM下面具有虚拟通孔，以防止在接合期间在凸块电池位置处的分层。虚设通孔插入到设计中，并且在铺设阶段期间以及在有源集成电路部件的放置和布线之前发生凸起电池放置。以这种方式，实现足够高的通孔密度，并且将包括虚拟通路的凸起单元的设计信息与用于执行所指示的设计操作序列的程序指令一起提供给计算机辅助设计CAD系统。

2. 发明申请

US20100242008A1 METHOD FOR DUMMY METAL AND DUMMY VIA INSERTION 有权
标题翻译：用于金属和DUMMY通过插入的方法
公开(公告)号：US20100242008A1
公开(公告)日：2010-09-23
申请号：US12728728
申请日：2010-03-22
申请人： Hung-Yi LIU , Chung-Hsing WANG , Chih-Chieh CHEN , Jian-Yi LI
发明人： Hung-Yi LIU , Chung-Hsing WANG , Chih-Chieh CHEN , Jian-Yi LI
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5045 , G06F17/5068 , G06F17/5072 , G06F17/5081
摘要： A method for dummy metal and dummy via insertion is provided. In one embodiment, dummy metals are inserted using a place and route tool, where the place and route tool has timing-awareness. Then, dummy vias arrays are inserted inside an overlap area of dummy metals using a design-rule-checking utility. Fine-grained dummy vias arrays are inserted in available space far away from main patterns. The dummy-patterns resulting from the inserted dummy vias are compressed using the design-rule-checking utility to reduce the size of a graphic data system file generated from the integrated circuit design. The dummy vias can be inserted with relaxed via spacing rules. The dummy metals are inserted with a constant line-end spacing between them for better process control and the maximum length of the dummy metal can be limited for smaller coupling effects. The dummy vias can have various sizes and a square or rectangular shape.
摘要翻译：提供了一种用于虚拟金属和虚拟通孔插入的方法。在一个实施例中，使用地点和路线工具插入虚拟金属，其中地点和路线工具具有时间意识。然后，使用设计规则检查实用程序将虚拟过孔阵列插入到虚拟金属的重叠区域内。细粒度的虚拟通孔阵列插入到远离主图案的可用空间中。使用设计规则检查实用程序对插入的虚拟通孔产生的虚拟模式进行压缩，以减小从集成电路设计生成的图形数据系统文件的大小。虚拟通孔可以放松通过间隔规则插入。虚拟金属以它们之间的恒定的线端间隔插入，以获得更好的工艺控制，并且可以限制虚拟金属的最大长度以减小耦合效应。虚拟通孔可以具有各种尺寸和正方形或矩形形状。

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