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    • 3. 发明授权
    • Synchronous signal generating method, recording apparatus, transmitting apparatus, recording medium, and transmission medium
    • 同步信号产生方法,记录装置,发送装置,记录介质和传输介质
    • US06898166B2
    • 2005-05-24
    • US10054786
    • 2002-01-25
    • Tsuyoshi OkiAtsushi Hayami
    • Tsuyoshi OkiAtsushi Hayami
    • G11B20/14G11B27/30H03M5/14H03M7/14H03M7/46H04L7/08H04L25/49G11B7/05H03M7/00
    • H03M7/46G11B20/1426G11B27/3027G11B2220/2562H03M5/145
    • There is disclosed a synchronous signal generating method, recording apparatus, transmitting apparatus, recording medium and transmission medium in which a plurality of coding tables is used to convert an input data word of p-bits to a code word of q-bits (q>p), and a code word string obtained by directly coupling the code words is recorded and reproduced in a recording medium such as an optical disk and magnetic disk, or transmitted via a transmitting portion. A synchronous frame consists of a synchronous signal and the cord word string satisfying restriction on minimum run length and maximum run length. The synchronous signal is separable from the code word string satisfying a predetermined run length restriction rule, and is constituted with a specific code for identifying its position in one sector, and a synchronous pattern consisting of a first bit pattern having a run length longer than the maximum run length of the predetermined run length restriction rule by 1T or more, and a following second bit pattern having a run length longer than the minimum run length.
    • 公开了一种同步信号生成方法,记录装置,发送装置,记录介质和传输介质,其中使用多个编码表将p位的输入数据字转换为q位的码字(q> p),并且通过直接耦合码字获得的码字串被记录和再现在诸如光盘和磁盘的记录介质中,或者经由发送部分发送。 同步帧由同步信号和绳字符串组成,满足最小游程长度和最大游程长度的限制。 该同步信号与满足规定游程长度限制规则的代码字串可分离,并且由用于识别其在一个扇区中的位置的特定代码构成,并且由具有长于该扇区长度的游程长度的第一位模式组成的同步模式 预定游程长度限制规则的最大游程长度为1T以上,以及具有比最小游程长度更长的游程长度的后续第二比特模式。
    • 4. 发明授权
    • Modulation method, modulation apparatus, demodulation method, demodulation apparatus, information recording medium, information transmission method, and information transmission apparatus
    • 调制方法,调制装置,解调方法,解调装置,信息记录介质,信息发送方法和信息发送装置
    • US06653952B2
    • 2003-11-25
    • US10160023
    • 2002-06-04
    • Atsushi HayamiToshio KuroiwaTsuyoshi Oki
    • Atsushi HayamiToshio KuroiwaTsuyoshi Oki
    • H03M700
    • H03M5/145G11B20/1426G11B2020/1282G11B2020/1284G11B2020/143G11B2020/1457H03M7/46
    • There is disclosed a modulation method in which a four bit unit of a plurality of continuous input data words is encoded into a six bit unit of a plurality of continuous output code words by referring to a plurality of coding tables including output code words corresponding to input data words, and coding table designation information in which a coding table for use in encoding the next input data word is designated. The plurality of coding tables includes at least a first coding table and a second coding table, and first and second signals respectively obtained by subjecting a first output code word of said first coding table corresponding to a predetermined input data word and a second output code word of said second coding table corresponding to said predetermined input data word to NRZI modulation are reverse to each other in polarity. Further, in particular, two redundant bits are inserted into the plurality of continuous output code words for each predetermined number of corresponding data words. Even with such redundant bits, a DSV control is performed in any section, k satisfies 9 in a (1, k) RLL rule, and a repetition frequency of a minimum run is limited.
    • 公开了一种调制方法,其中通过参考包括与输入对应的输出代码字的多个编码表,将多个连续输入数据字中的四位单位编码为多个连续输出代码字的六位单元 数据字和编码表指定信息,其中指定用于编码下一个输入数据字的编码表。 多个编码表至少包括第一编码表和第二编码表,以及分别通过对与预定输入数据字对应的所述第一编码表的第一输出代码字和第二输出代码字 对应于所述预定输入数据字到NRZI调制的所述第二编码表的极性相反。 此外,特别地,对于每个预定数量的相应数据字,两个冗余比特被插入到多个连续输出码字中。 即使使用这样的冗余比特,在任何部分都执行DSV控制,在(1,k)RLL规则中k满足9,并且限制最小运行的重复频率。
    • 7. 发明授权
    • Method of detecting sync signals
    • 检测同步信号的方法
    • US07586820B2
    • 2009-09-08
    • US11264015
    • 2005-11-02
    • Tsuyoshi Oki
    • Tsuyoshi Oki
    • G11B7/00
    • G11B20/1403G11B7/0053G11B27/105G11B27/24G11B27/3027
    • A pattern of an input sync signal is compared with sub patterns in a first sync pattern. The sub patterns in the first sync pattern are equal to the patterns of true sync signals, respectively. When the pattern of the input sync signal agrees with none of the sub patterns in the first sync pattern, the pattern of the input sync signal is compared with sub patterns in a second sync pattern. The sub patterns in the second sync pattern have temporal fluctuations with respect to the patterns of the true sync signals. Each of the sub patterns in the second sync pattern is assigned to only one of the true sync signals. It is determined that a sync signal is detected when the pattern of the input sync signal agrees with one of the sub patterns in the first and second sync patterns.
    • 将输入同步信号的模式与第一同步模式中的子模式进行比较。 第一同步模式中的子模式分别等于真同步信号的模式。 当输入同步信号的模式与第一同步模式中的任何子模式不一致时,将输入同步信号的模式与第二同步模式中的子模式进行比较。 第二同步图案中的子图案相对于真同步信号的图案具有时间波动。 第二同步模式中的每个子模式被分配给仅一个真同步信号。 当输入同步信号的模式与第一和第二同步模式中的一个子模式一致时,确定同步信号被检测到。
    • 9. 发明授权
    • Viterbi decoder and Viterbi decoding method
    • 维特比解码器和维特比解码方法
    • US06819724B2
    • 2004-11-16
    • US09737597
    • 2000-12-18
    • Atsushi HayamiTsuyoshi Oki
    • Atsushi HayamiTsuyoshi Oki
    • H04D100
    • H03M13/6331G11B20/10009H03M13/3961H03M13/41H03M13/6343
    • A data estimating circuit outputs estimation data which estimates input data at a time earlier by a predetermined bit cycle than the input data based on decoded data series outputted from a path memory. A target value computing circuit corrects the target value with a difference between the estimation data and input data as a target value error and outputs obtained plural first target values to a branchmetric operating circuit as plural target values. Because the branchmetric operating circuit can conduct branchmetric operation based on plural first target values near plural averages having the highest incidence (having peaks in histogram), decoding performance can be improved more as compared to using fixed target values.
    • 数据估计电路输出基于从路径存储器输出的解码数据序列,输出预测数据比预定的位周期预测输入数据的估计数据。 目标值计算电路用估计数据和输入数据之间的差作为目标值误差来校正目标值,并将获得的多个第一目标值作为多个目标值输出到分支操作电路。 由于分支操作电路可以基于具有最高入射角(具有直方图峰值)的多个平均值附近的多个第一目标值进行支路测量操作,所以与使用固定目标值相比,可以更好地提高解码性能。