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1. 发明授权

US5412615A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5412615A
公开(公告)日：1995-05-02
申请号：US166099
申请日：1993-12-14
申请人： Hiromi Noro , Shinnosuke Kamata , Yoshinori Okajima
发明人： Hiromi Noro , Shinnosuke Kamata , Yoshinori Okajima
IPC分类号： G06F9/38 , G11C7/22 , G11C11/407 , G11C11/413 , G11C11/417 , G11C8/00
CPC分类号： G11C7/225 , G11C7/22
摘要： This invention provides an apparatus in which a time difference between an eternal clock signal and an internal clock signal is eliminated, and in which a high operation speed even at a high operation frequency is accomplished without causing erroneous circuit operations. A semiconductor integrated circuit device is equipped with a signal generator for generating an internal clock signal for determining an operation timing of an internal circuit from an external clock signal. The semiconductor integrated circuit device includes a delay unit for bringing an edge of the external clock signal into conformity with the edge of the internal clock signal by delaying the output of the signal generator by the time obtained by subtracting a time corresponding to a circuit delay of the signal generator from a time corresponding to some integral multiple of a 1/2 cycle of the external clock signal.
摘要翻译：本发明提供一种其中消除了永恒时钟信号和内部时钟信号之间的时间差的装置，并且其中即使在高操作频率下也实现高运行速度而不引起错误的电路操作。半导体集成电路器件配备有信号发生器，用于产生用于从外部时钟信号确定内部电路的操作定时的内部时钟信号。半导体集成电路器件包括延迟单元，用于通过将信号发生器的输出延迟通过减去与电路延迟相对应的时间而获得的时间，使得外部时钟信号的边沿与内部时钟信号的边缘一致信号发生器从对应于外部时钟信号的1/2周期的一些整数倍的时间开始。

2. 发明授权

US07085147B2 Systems and methods for preventing malfunction of content addressable memory resulting from concurrent write and lookup operations 有权
标题翻译：用于防止由并发写入和查找操作导致的内容可寻址内存故障的系统和方法
公开(公告)号：US07085147B2
公开(公告)日：2006-08-01
申请号：US11003084
申请日：2004-12-03
申请人： Hiroaki Murakami , Hiromi Noro , Osamu Takahashi
发明人： Hiroaki Murakami , Hiromi Noro , Osamu Takahashi
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： Systems and methods for preventing the corruption of a CAM lookup result when a lookup in the CAM and a write to the CAM are concurrently executed. In one embodiment, a tag value is clocked into a tag latch simultaneously with a data value being clocked into a data latch. The tag value and initial CAM element values begin propagating through comparison logic. After a delay, the data value is written from the data latch to a CAM element. After the tag value and initial CAM values propagate through the comparison logic to produce comparison outputs, but before the newly written data value propagates through the comparison logic and changes the comparison outputs, the comparison outputs are latched. The comparison outputs can then be processed as if the data values in the CAM elements had not been changed by the write operation.
摘要翻译：当CAM中的查找和对CAM的写入被同时执行时，用于防止CAM查找的损坏的系统和方法。在一个实施例中，将标签值与被计入数据锁存器的数据值同时定时到标签锁存器中。标签值和初始CAM元素值通过比较逻辑开始传播。在延迟之后，将数据值从数据锁存器写入CAM元件。在标签值和初始CAM值通过比较逻辑传播以产生比较输出之后，但在新写入的数据值通过比较逻辑传播并更改比较输出之前，比较输出被锁存。然后可以像比较输出那样处理，因为CAM元素中的数据值没有被写入操作改变。

3. 发明申请

US20120195109A1 SEMICONDUCTOR STORAGE DEVICE 审中-公开
标题翻译：半导体存储设备
公开(公告)号：US20120195109A1
公开(公告)日：2012-08-02
申请号：US13237251
申请日：2011-09-20
申请人： Hiromi Noro
发明人： Hiromi Noro
IPC分类号： G11C11/412 , G11C7/08
CPC分类号： G11C7/08 , G11C7/227 , G11C11/419
摘要： According to one embodiment, a sense amplifier detects data stored in a memory cell based on potentials of bit lines of a bit line pair where bit line pairs are provided to correspond to columns of a memory cell array, respectively. Dummy cells are provided to correspond to rows of the memory cell array, respectively to simulate a read operation of the memory cells. A dummy bit line pair is driven in a complementary manner based on data read from the dummy cell. A read control unit controls the read operation of the memory cells based on the potential difference between dummy bit lines of the dummy bit line pair.
摘要翻译：根据一个实施例，读出放大器基于分别对应于存储单元阵列的列的位线对的位线对的位线的电位来检测存储在存储单元中的数据。分别提供虚拟单元以对应于存储单元阵列的行以模拟存储器单元的读取操作。基于从虚拟单元读取的数据，以互补的方式驱动虚拟位线对。读取控制单元基于虚拟位线对的虚拟位线之间的电位差来控制存储器单元的读取操作。

4. 发明申请

US20060120127A1 SYSTEMS AND METHODS FOR PREVENTING MALFUNCTION OF CONTENT ADDRESSABLE MEMORY RESULTING FROM CONCURRENT WRITE AND LOOKUP OPERATIONS 有权
标题翻译：用于防止来自同时写入和查找操作的内容可寻址存储器的故障的系统和方法
公开(公告)号：US20060120127A1
公开(公告)日：2006-06-08
申请号：US11003084
申请日：2004-12-03
申请人： Hiroaki Murakami , Hiromi Noro , Osamu Takahashi
发明人： Hiroaki Murakami , Hiromi Noro , Osamu Takahashi
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： Systems and methods for preventing the corruption of a CAM lookup result when a lookup in the CAM and a write to the CAM are concurrently executed. In one embodiment, a tag value is clocked into a tag latch simultaneously with a data value being clocked into a data latch. The tag value and initial CAM element values begin propagating through comparison logic. After a delay, the data value is written from the data latch to a CAM element. After the tag value and initial CAM values propagate through the comparison logic to produce comparison outputs, but before the newly written data value propagates through the comparison logic and changes the comparison outputs, the comparison outputs are latched. The comparison outputs can then be processed as if the data values in the CAM elements had not been changed by the write operation.
摘要翻译：当CAM中的查找和对CAM的写入被同时执行时，用于防止CAM查找的损坏的系统和方法。在一个实施例中，将标签值与被计入数据锁存器的数据值同时定时到标签锁存器中。标签值和初始CAM元素值通过比较逻辑开始传播。在延迟之后，将数据值从数据锁存器写入CAM元件。在标签值和初始CAM值通过比较逻辑传播以产生比较输出之后，但在新写入的数据值通过比较逻辑传播并更改比较输出之前，比较输出被锁存。然后可以像比较输出那样处理，因为CAM元素中的数据值没有被写入操作改变。

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