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1. 发明授权

US06611464B2 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics 失效
公开(公告)号：US06611464B2
公开(公告)日：2003-08-26
申请号：US10265233
申请日：2002-10-07
申请人： Takao Akaogi , Nobuaki Takashina , Yasushi Kasa , Kiyoshi Itano , Hiromi Kawashima , Minoru Yamashita , Shouichi Kawamura
发明人： Takao Akaogi , Nobuaki Takashina , Yasushi Kasa , Kiyoshi Itano , Hiromi Kawashima , Minoru Yamashita , Shouichi Kawamura
IPC分类号： G11C1604
CPC分类号： G11C29/80 , G11C5/145 , G11C7/067 , G11C8/00 , G11C8/08 , G11C8/10 , G11C16/04 , G11C16/0416 , G11C16/08 , G11C16/10 , G11C16/107 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3404 , G11C16/3409 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C16/3472 , G11C16/3481 , G11C29/028 , G11C29/34 , G11C29/46 , G11C29/50 , G11C29/50004 , G11C29/802 , G11C29/82 , G11C29/88 , G11C2029/5004
摘要： A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

2. 发明授权

US5666314A Semiconductor memory device for selecting and deselecting blocks of word lines 失效
标题翻译：用于选择和取消选择字线块的半导体存储器件
公开(公告)号：US5666314A
公开(公告)日：1997-09-09
申请号：US432723
申请日：1995-06-06
申请人： Takao Akaogi , Nobuaki Takashina , Yasushi Kasa , Kiyoshi Itano , Hiromi Kawashima , Minoru Yamashita
发明人： Takao Akaogi , Nobuaki Takashina , Yasushi Kasa , Kiyoshi Itano , Hiromi Kawashima , Minoru Yamashita
IPC分类号： G11C5/14 , G11C7/06 , G11C8/00 , G11C8/08 , G11C8/10 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/34 , G11C29/00 , G11C29/34 , G11C29/46 , G11C29/50 , G11C7/00
CPC分类号： G11C29/80 , G11C16/08 , G11C16/10 , G11C16/107 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3404 , G11C16/3409 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C16/3472 , G11C16/3481 , G11C29/028 , G11C29/34 , G11C29/46 , G11C29/50 , G11C29/50004 , G11C29/802 , G11C29/82 , G11C5/145 , G11C7/067 , G11C8/00 , G11C8/08 , G11C8/10 , G11C16/04 , G11C16/0416 , G11C2029/5004 , G11C29/88
摘要： A semiconductor memory device has 2.sup.n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2.sup.m (n>m) word lines among the 2.sup.n word lines, and a second unit for not selecting a block of 2.sup.k (m>k) word lines among the 2.sup.m word lines. The second unit does not select the block of 2.sup.k word lines, and selects a block of 2.sup.k word lines prepared outside the 2" word lines when any one of the 2.sup.k word lines among the 2.sup.m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.
摘要翻译：半导体存储器件具有2n字线，多个位线，设置在字线和位线的每个交叉处的多个非易失性存储器单元，写入电路用于将数据写入位于所选择的交叉点的存储器单元字线和位线中的一个以及用于从存储器单元读出数据的读出放大器。此外，半导体存储装置包括：第一单元，用于同时选择2n个字线中的2m（n> m）个字线的块;以及第二单元，用于不选择2k（m> k）个字线的块， 2m字线。第二单元不选择2k个字线的块，并且当2m个字线中的任何2k个字线中的任何一个有缺陷时，选择2K字线以外准备的2k个字线的块。因此，有效地使用冗余字线，写入和验证操作是稳定的，从而提高半导体存储器件的产量和性能。

3. 发明授权

US5631597A Negative voltage circuit for a flash memory 失效
标题翻译：闪存的负电压电路
公开(公告)号：US5631597A
公开(公告)日：1997-05-20
申请号：US445103
申请日：1995-05-19
申请人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
发明人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
IPC分类号： G05F3/20 , G11C5/14 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/16 , G11C16/30 , G11C29/00 , H03K3/356 , H03K19/0185 , H03K19/21 , G05F1/10
CPC分类号： G11C29/82 , G05F3/205 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , G11C5/145 , H03K19/018521 , H03K19/215 , H03K3/356147 , H03K3/356165
摘要： A negative-voltage circuit for realizing a flash memory is installed independently and is applied selectively to word lines in response to signals sent from row decoders. Row decoders for specifying word lines need not be installed in the negative voltage circuit. The negative circuit can therefore be reduced in scale.
摘要翻译：独立地安装用于实现闪速存储器的负电压电路，并响应于从行解码器发送的信号而选择性地对字线施加。用于指定字线的行解码器不需要安装在负电压电路中。因此，可以减小负电路的规模。

4. 发明授权

US5428580A Nonvolatile semiconductor memory having an address-transition-detection circuit 失效
标题翻译：具有地址转换检测电路的非易失性半导体存储器
公开(公告)号：US5428580A
公开(公告)日：1995-06-27
申请号：US176431
申请日：1994-01-03
申请人： Hiromi Kawashima , Takao Akaogi
发明人： Hiromi Kawashima , Takao Akaogi
IPC分类号： G11C16/02 , G11C5/14 , G11C16/06 , G11C16/30 , G11C16/34 , H01L21/8247 , H01L27/115 , G11C7/00
CPC分类号： G11C16/3445 , G11C16/30 , G11C16/3436 , G11C16/3459 , G11C5/143
摘要： The object of the present invention is to provide a nonvolatile memory wherein stored data can be properly read at power-on even if the memory is designed to achieve faster operating speeds by performing operations such as bit line charge-up by detecting an address signal change and the turning-on of the power. A nonvolatile semiconductor memory in which, after a write or an erase operation, a read operation for verification is performed by applying a voltage at a first verification level V2, which is lower than an applied voltage for a normal read operation, or a voltage at a second verification level V3, which is higher than the applied voltage V1, the nonvolatile semiconductor memory comprising: an address-transition-detection circuit 1; a supply voltage detection circuit 3 for generating an initialization transition signal at the rise of a supply voltage when the supply voltage has reached a first supply voltage transition threshold level V4 higher than the first verification level V2; and a transition operation circuit 2 for performing operations such as bit line charge-up in accordance with the address transition signal and initialization transition signal.
摘要翻译：本发明的目的是提供一种非易失性存储器，其中存储的数据可以在上电时被适当地读取，即使存储器被设计为通过通过检测地址信号变化来执行诸如位线充电的操作来实现更快的操作速度并开启电源。一种非易失性半导体存储器，其中，在写入或擦除操作之后，通过施加低于正常读取操作的施加电压的第一验证电平V2或者正常读取操作的电压来执行用于验证的读取操作第二验证电平V3高于施加的电压V1，非易失性半导体存储器包括：地址转换检测电路1; 电源电压检测电路3，用于当电源电压达到高于第一验证电平V2的第一电源电压转变阈值电平V4时，在电源电压上升时产生初始化转换信号; 以及用于根据地址转换信号和初始化转换信号执行诸如位线充电的操作的转换操作电路2。

5. 发明授权

US4773046A Semiconductor device having fuse circuit and detecting circuit for detecting states of fuses in the fuse circuit 失效
标题翻译：具有熔丝电路的半导体装置和用于检测熔丝电路中熔丝状态的检测电路
公开(公告)号：US4773046A
公开(公告)日：1988-09-20
申请号：US60018
申请日：1987-06-09
申请人： Takao Akaogi , Hiromi Kawashima
发明人： Takao Akaogi , Hiromi Kawashima
IPC分类号： G11C17/16 , G11C17/18 , G11C29/00 , G11C29/04 , G11C13/00 , G11C11/36
CPC分类号： G11C29/785 , G11C17/16 , G11C17/18 , G11C29/835
摘要： A semiconductor device comprises a fuse circuit having first and second fuses for storing an information bit represented by blown or unblown states of the fuses. The device uses an information output circuit for providing an output signal having a first logic level when at least one of the fuses is blown and an output signal having a second logic level when both the fuses are unblown. A detecting circuit in the device detects which one of the fuses is unblown.
摘要翻译：一种半导体器件包括具有第一和第二熔丝的熔丝电路，用于存储由保险丝的熔断状态或非吹制状态所表示的信息位。当熔丝中的至少一个熔断时，该装置使用信息输出电路来提供具有第一逻辑电平的输出信号，并且当两个保险丝都未被吹出时，该装置具有具有第二逻辑电平的输出信号。该装置中的检测电路检测哪个保险丝未被吹出。

6. 发明授权

US06563738B2 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics 失效
公开(公告)号：US06563738B2
公开(公告)日：2003-05-13
申请号：US10150017
申请日：2002-05-20
申请人： Takao Akaogi , Nobuaki Takashina , Yasushi Kasa , Kiyoshi Itano , Hiromi Kawashima , Minoru Yamashita
发明人： Takao Akaogi , Nobuaki Takashina , Yasushi Kasa , Kiyoshi Itano , Hiromi Kawashima , Minoru Yamashita
IPC分类号： G11C1604
CPC分类号： G11C29/80 , G11C5/145 , G11C7/067 , G11C8/00 , G11C8/08 , G11C8/10 , G11C16/04 , G11C16/0416 , G11C16/08 , G11C16/10 , G11C16/107 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3404 , G11C16/3409 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C16/3472 , G11C16/3481 , G11C29/028 , G11C29/34 , G11C29/46 , G11C29/50 , G11C29/50004 , G11C29/802 , G11C29/82 , G11C29/88 , G11C2029/5004
摘要： A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

7. 发明授权

US5608670A Flash memory with improved erasability and its circuitry 失效
标题翻译：闪存具有改进的可擦除性及其电路
公开(公告)号：US5608670A
公开(公告)日：1997-03-04
申请号：US436721
申请日：1995-05-08
申请人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
发明人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
IPC分类号： G05F3/20 , G11C5/14 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/16 , G11C16/30 , G11C29/00 , H03K3/356 , H03K19/0185 , H03K19/21
CPC分类号： G11C29/82 , G05F3/205 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , G11C5/145 , H03K19/018521 , H03K19/215 , H03K3/356147 , H03K3/356165
摘要： The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective transistors simultaneously.
摘要翻译：本发明涉及擦除闪存的改进。本发明的目的是缩短擦除时间。在预擦除写入期间，一次以多行单位选择字线或位线中的至少一个，并且数据被同时写入多个选择晶体管。

8. 发明授权

US5770963A Flash memory with improved erasability and its circuitry 失效
标题翻译：闪存具有改进的可擦除性及其电路
公开(公告)号：US5770963A
公开(公告)日：1998-06-23
申请号：US436699
申请日：1995-05-08
申请人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
发明人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
IPC分类号： G05F3/20 , G11C5/14 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/16 , G11C16/30 , G11C29/00 , H03K3/356 , H03K19/0185 , H03K19/21 , H03K5/08
CPC分类号： G11C29/82 , G05F3/205 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , G11C5/145 , H03K19/018521 , H03K19/215 , H03K3/356147 , H03K3/356165
摘要： A flash memory performs channel erasing or source erasing by applying a negative voltage to a control gate. The device includes a voltage restriction device which restricts the negative voltage to be applied to the control gate so that the negative voltage will be a constant value relative to the voltage of the channel or source. Alternatively, two voltage restricting devices restrict the negative voltage applied to the control gate and the voltage to be applied to the source so that the voltages will be a constant value relative to a common reference voltage.
摘要翻译：闪存通过向控制栅极施加负电压来执行信道擦除或源擦除。该装置包括限制施加到控制栅极的负电压的电压限制装置，使得负电压相对于通道或源的电压将是恒定值。或者，两个电压限制装置限制施加到控制栅极的负电压和施加到源极的电压，使得电压相对于公共参考电压将是恒定值。

9. 发明授权

US5592419A Flash memory with improved erasability and its circuitry 失效
公开(公告)号：US5592419A
公开(公告)日：1997-01-07
申请号：US441598
申请日：1995-05-15
申请人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
发明人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
IPC分类号： G05F3/20 , G11C5/14 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/16 , G11C16/30 , G11C29/00 , H03K3/356 , H03K19/0185 , H03K19/21
CPC分类号： G11C29/82 , G05F3/205 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , G11C5/145 , H03K19/018521 , H03K19/215 , H03K3/356147 , H03K3/356165
摘要： The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective transistors simultaneously.

10. 发明授权

US5452251A Semiconductor memory device for selecting and deselecting blocks of word lines 失效
标题翻译：用于选择和取消选择字线块的半导体存储器件
公开(公告)号：US5452251A
公开(公告)日：1995-09-19
申请号：US79738
申请日：1993-06-22
申请人： Takao Akaogi , Nobuaki Takashina , Yasushi Kasa , Kiyoshi Itano , Hiromi Kawashima , Minoru Yamashita
发明人： Takao Akaogi , Nobuaki Takashina , Yasushi Kasa , Kiyoshi Itano , Hiromi Kawashima , Minoru Yamashita
IPC分类号： G11C5/14 , G11C7/06 , G11C8/00 , G11C8/08 , G11C8/10 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/34 , G11C29/00 , G11C29/34 , G11C29/46 , G11C29/50 , G11C11/40
CPC分类号： G11C29/80 , G11C16/08 , G11C16/10 , G11C16/107 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3404 , G11C16/3409 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C16/3472 , G11C16/3481 , G11C29/028 , G11C29/34 , G11C29/46 , G11C29/50 , G11C29/50004 , G11C29/802 , G11C29/82 , G11C5/145 , G11C7/067 , G11C8/00 , G11C8/08 , G11C8/10 , G11C16/04 , G11C16/0416 , G11C2029/5004 , G11C29/88
摘要： A semiconductor memory device has 2.sup.n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2.sup.m (n>m) word lines among the 2.sup.n word lines, and a second unit for not selecting a block of 2.sup.k (m>k) word lines among the 2.sup.m word lines. The second unit does not select the block of 2.sup.k word lines, and selects a block of 2.sup.k word lines prepared outside the 2.sup.n word lines when any one of the 2.sup.k word lines among the 2.sup.m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.
摘要翻译：半导体存储器件具有2n字线，多个位线，设置在字线和位线的每个交叉处的多个非易失性存储器单元，写入电路用于将数据写入位于所选择的交叉点的存储器单元字线和位线中的一个以及用于从存储器单元读出数据的读出放大器。此外，半导体存储装置包括：第一单元，用于同时选择2n个字线中的2m（n> m）个字线的块;以及第二单元，用于不选择2k（m> k）个字线的块， 2m字线。第二单元不选择2k个字线的块，并且当2m个字线中的任何2k个字线中的任一个有缺陷时，选择在2n个字线之外准备的2k个字线的块。因此，有效地使用冗余字线，写入和验证操作是稳定的，从而提高半导体存储器件的产量和性能。

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