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1. 发明申请

US20090033431A1 Oscillation Circuit 审中-公开
标题翻译：振荡电路
公开(公告)号：US20090033431A1
公开(公告)日：2009-02-05
申请号：US12182171
申请日：2008-07-30
申请人： Hiroki Yamashita , Koji Fukuda , Ryo Nemoto , Hisaaki Kanai , Keiichi Yamamoto
发明人： Hiroki Yamashita , Koji Fukuda , Ryo Nemoto , Hisaaki Kanai , Keiichi Yamamoto
IPC分类号： H03K3/03
CPC分类号： H03K3/0322
摘要： The present invention provides a highly accurate oscillation circuit. For example, the oscillation circuit includes plural ring oscillator units RO1 and RO2 including inverter circuits IV of an odd number of stages, and an adding unit ADD that adds signals of output nodes RO—01 and RO—02 of the RO1 and RO2. It outputs an addition result of the ADD from an output node OSC_O as a clock signal, and feeds the output node OSC_O back to input nodes RO_I1 and RO_I2 of the RO1 and RO2. Thereby, for example, when each of delay times of the RO1 and RO2 disperses based on a normal distribution of standard deviation σ, the dispersion of a clock signal obtained from the OSC_O can be confined to σ/√{square root over (2)}.
摘要翻译：本发明提供了一种高精度的振荡电路。例如，振荡电路包括包含奇数级的反相器电路IV的多个环形振荡器单元RO1和RO2，以及将RO1和RO2的输出节点RO-01和RO-02的信号相加的相加单元ADD。它从输出节点OSC_O输出ADD的相加结果作为时钟信号，并将输出节点OSC_O反馈给RO1和RO2的输入节点RO_I1和RO_I2。因此，例如，当RO1和RO2的每个延迟时间基于标准偏差Σ的正态分布而分散时，从OSC_O获得的时钟信号的色散可以被限制为sigma /√{ }。

2. 发明授权

US07649381B2 Level conversion circuit 有权
标题翻译：电平转换电路
公开(公告)号：US07649381B2
公开(公告)日：2010-01-19
申请号：US12000608
申请日：2007-12-14
申请人： Hiroki Yamashita , Fumio Yuuki , Ryo Nemoto , Hisaaki Kanai , Keiichi Yamamoto
发明人： Hiroki Yamashita , Fumio Yuuki , Ryo Nemoto , Hisaaki Kanai , Keiichi Yamamoto
IPC分类号： H03K19/094
CPC分类号： H03K19/094 , H03K19/018521
摘要： A level conversion circuit capable of realizing low-power/high-speed operation and suppression of variations in input/output characteristics due to variations in source voltage and temperature and device variation. The level conversion circuit comprises: a source follower circuit including a first transistor to input an AC signal of CML level thereto and a second transistor to input a control voltage thereto; and a control-voltage generating circuit to generate the control voltage to be inputted to the second transistor. The control-voltage generating circuit comprises: a replica source follower circuit which is a replica of the source follower circuit including a third transistor to input a central voltage of CML level thereto and a fourth transistor to input the control voltage thereto; and a comparator which controls the control voltage, thereby equalizing an output voltage of the replica source follower and a threshold voltage of a CMOS circuit.
摘要翻译：一种能够实现低功率/高速操作并且抑制由于源电压和温度以及器件变化的变化而导致的输入/输出特性变化的电平转换电路。电平转换电路包括：源极跟随器电路，包括用于向其输入CML电平的AC信号的第一晶体管和向其输入控制电压的第二晶体管; 以及控制电压产生电路，用于产生要输入到第二晶体管的控制电压。控制电压产生电路包括：复制源跟随器电路，其是源极跟随器电路的副本，其包括用于输入CML电平的中心电压的第三晶体管和向其输入控制电压的第四晶体管; 以及控制控制电压的比较器，从而使复制源极跟随器的输出电压和CMOS电路的阈值电压相等。

3. 发明申请

US20080157816A1 Level conversion circuit 有权
标题翻译：电平转换电路
公开(公告)号：US20080157816A1
公开(公告)日：2008-07-03
申请号：US12000608
申请日：2007-12-14
申请人： Hiroki Yamashita , Fumio Yuuki , Ryo Nemoto , Hisaaki Kanai , Keiichi Yamamoto
发明人： Hiroki Yamashita , Fumio Yuuki , Ryo Nemoto , Hisaaki Kanai , Keiichi Yamamoto
IPC分类号： H03K19/094
CPC分类号： H03K19/094 , H03K19/018521
摘要： A level conversion circuit capable of realizing low-power/high-speed operation and suppression of variations in input/output characteristics due to variations in source voltage and temperature and device variation. The level conversion circuit comprises: a source follower circuit including a first transistor to input an AC signal of CML level thereto and a second transistor to input a control voltage thereto; and a control-voltage generating circuit to generate the control voltage to be inputted to the second transistor. The control-voltage generating circuit comprises: a replica source follower circuit which is a replica of the source follower circuit including a third transistor to input a central voltage of CML level thereto and a fourth transistor to input the control voltage thereto; and a comparator which controls the control voltage, thereby equalizing an output voltage of the replica source follower and a threshold voltage of a CMOS circuit.
摘要翻译：一种能够实现低功率/高速操作并且抑制由于源电压和温度和器件变化的变化而导致的输入/输出特性变化的电平转换电路。电平转换电路包括：源极跟随器电路，包括用于向其输入CML电平的AC信号的第一晶体管和向其输入控制电压的第二晶体管; 以及控制电压产生电路，用于产生要输入到第二晶体管的控制电压。控制电压产生电路包括：复制源跟随器电路，其是源极跟随器电路的副本，其包括用于输入CML电平的中心电压的第三晶体管和向其输入控制电压的第四晶体管; 以及控制控制电压的比较器，从而使复制源极跟随器的输出电压和CMOS电路的阈值电压相等。

4. 发明授权

US07902860B2 Semiconductor circuit, and computing device and communications device using the same 有权
标题翻译：半导体电路，以及使用它的计算设备和通信设备
公开(公告)号：US07902860B2
公开(公告)日：2011-03-08
申请号：US12145829
申请日：2008-06-25
申请人： Keiichi Yamamoto , Norio Chujo , Toru Yazaki , Hisaaki Kanai
发明人： Keiichi Yamamoto , Norio Chujo , Toru Yazaki , Hisaaki Kanai
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03F3/3028 , H01L2924/19051 , H03F1/308 , H03F2200/447 , H03F2200/453 , H03K19/017581
摘要： In a semiconductor circuit, an impedance adjustment circuit having the characteristics same as those of a circuit having the nonlinear resistance characteristics is configured to include an operating point calculation circuit automatically calculating an operating point with a reference resistance through feedback control, and an impedance calculation circuit calculating the impedance at the operating point found by the operating point calculation circuit. The impedance adjustment circuit is also provided with an impedance determination circuit that determines whether or not the impedance found by the impedance calculation circuit is in a predetermined range. These components, i.e., the operating point calculation circuit, the impedance calculation circuit, and the impedance determination circuit, are provided each two for High-side and Low-side impedance adjustment use.
摘要翻译：在半导体电路中，具有与具有非线性电阻特性的电路相同特性的阻抗调整电路被配置为包括工作点计算电路，通过反馈控制自动计算具有参考电阻的工作点，以及阻抗计算电路计算由工作点计算电路找到的工作点处的阻抗。阻抗调整电路还设置有阻抗确定电路，其确定由阻抗计算电路发现的阻抗是否在预定范围内。这两个部件，即工作点计算电路，阻抗计算电路和阻抗确定电路，每两个用于高侧和低侧阻抗调节。

5. 发明授权

US07772877B2 Output buffer circuit, differential output buffer circuit, output buffer circuit having regulation circuit and regulation function, and transmission method 有权
标题翻译：输出缓冲电路，差分输出缓冲电路，具有调节电路和调节功能的输出缓冲电路及传输方式
公开(公告)号：US07772877B2
公开(公告)日：2010-08-10
申请号：US12343521
申请日：2008-12-24
申请人： Norio Chujo , Keiichi Yamamoto , Hisaaki Kanai , Toru Yazaki
发明人： Norio Chujo , Keiichi Yamamoto , Hisaaki Kanai , Toru Yazaki
IPC分类号： H03K19/003
CPC分类号： H04L25/0278 , H04L25/028
摘要： An output buffer circuit, a differential output buffer circuit, an output buffer circuit having a regulation circuit and a regulation function, and a transmission method, to improve resolution of a pre-emphasis amount without increasing power consumption or a circuit area. The output buffer includes a delay circuit, an inverter and output buffers to transmit a logical signal to a transmission line and generate a waveform having four or more types of signal voltages on a transmission side according to a signal attenuation amount of the transmission line. The output buffer has a selector and a variable resistance portion at an output resistance to change a pre-emphasis amount according to a change in a variable resistance value. The inverter is configured to select a signal to input into the output buffer, invert a data signal and adjust a tap pre-emphasis amount by a select signal of the selector logic.
摘要翻译：输出缓冲电路，差分输出缓冲电路，具有调节电路和调节功能的输出缓冲电路以及传输方法，以提高预加重量的分辨率，而不增加功耗或电路面积。输出缓冲器包括延迟电路，反相器和输出缓冲器，以将逻辑信号传输到传输线，并根据传输线的信号衰减量产生在发送侧具有四种或更多种类型的信号电压的波形。输出缓冲器具有输出电阻的选择器和可变电阻部分，以根据可变电阻值的变化改变预加重量。逆变器被配置为选择要输入到输出缓冲器的信号，反转数据信号并通过选择器逻辑的选择信号调整抽头预加重量。

6. 发明申请

US20090179666A1 OUTPUT BUFFER CIRCUIT, DIFFERENTIAL OUTPUT BUFFER CIRCUIT, OUTPUT BUFFER CIRCUIT HAVING REGULATION CIRCUIT AND REGULATION FUNCTION, AND TRANSMISSION METHOD 有权
标题翻译：输出缓冲电路，差分输出缓冲电路，具有调节电路和调节功能的输出缓冲电路及传输方式
公开(公告)号：US20090179666A1
公开(公告)日：2009-07-16
申请号：US12343521
申请日：2008-12-24
申请人： Norio Chujo , Keiichi Yamamoto , Hisaaki Kanai , Toru Yazaki
发明人： Norio Chujo , Keiichi Yamamoto , Hisaaki Kanai , Toru Yazaki
IPC分类号： H03K19/003 , H03K19/0175
CPC分类号： H04L25/0278 , H04L25/028
摘要： An output buffer circuit, a differential output buffer circuit, an output buffer circuit having a regulation circuit and a regulation function, and a transmission method, capable of improving resolution of a pre-emphasis amount without increasing power consumption or a circuit area, in which the output buffer circuit 10 has a function which includes a delay circuit 23, an inverter 22 and output buffers 3 to 7 to transmit a logical signal to a transmission line 2 and generate a waveform having four or more types of signal voltages on a transmission side according to a signal attenuation amount of the transmission line 2 and the output buffer 3 has a variable resistance portion 12 at an on-resistance to change a pre-emphasis amount according to a change in a variable resistance value. The output buffer 3 has a selector 20 on a forward stage and a variable resistance portion 12 at an on-resistance. The inverter 22 is configured to select a signal to be input into the output buffer 6 according to a selector logic, invert a data signal and adjust a tap pre-emphasis amount by a select signal of the selector logic.
摘要翻译：输出缓冲电路，差分输出缓冲电路，具有调节电路和调节功能的输出缓冲电路以及传输方法，能够提高预加重量的分辨率而不增加功耗或电路面积，其中输出缓冲电路10具有包括延迟电路23，反相器22和输出缓冲器3〜7的功能，以将逻辑信号发送到传输线2，并在发送侧产生具有四种或更多种信号电压的波形根据传输线2的信号衰减量，输出缓冲器3具有导通电阻的可变电阻部分12，以根据可变电阻值的变化改变预加重量。输出缓冲器3具有前级上的选择器20和导通电阻的可变电阻部分12。反相器22被配置为根据选择器逻辑选择要输入到输出缓冲器6的信号，反转数据信号，并通过选择器逻辑的选择信号来调整抽头预加重量。

7. 发明授权

US09096878B2 Expression vector for producing protein derived from foreign gene in large quantity using animal cells, and use thereof 有权
标题翻译：用于使用动物细胞大量生产来自外来基因的蛋白质的表达载体及其用途
公开(公告)号：US09096878B2
公开(公告)日：2015-08-04
申请号：US13140905
申请日：2009-12-22
申请人： Hiroshi Tahara , Yusuke Suzuki , Keiichi Yamamoto , Yuzuru Kitahara , Yasuhiko Suzuki
发明人： Hiroshi Tahara , Yusuke Suzuki , Keiichi Yamamoto , Yuzuru Kitahara , Yasuhiko Suzuki
IPC分类号： C12P21/02 , C12N15/85
CPC分类号： C12P21/02 , C12N15/85 , C12N2830/00
摘要： The present inventors conducted dedicated studies and successfully constructed expression vectors that enable high-level production of foreign gene-derived proteins in mammalian host cells, which comprise a translation-impaired dihydrofolate reductase gene cistron whose expression has been attenuated by altering the codons to the least frequently used codons in mammals; and a gene cassette which has a cloning site for incorporation of a foreign gene between a highly transcriptionally active promoter and a highly stable polyadenylation signal.
摘要翻译：本发明人进行了专门研究并成功构建了能够在哺乳动物宿主细胞中高水平生产外源基因衍生蛋白质的表达载体，其包含翻译受损的二氢叶酸还原酶基因顺反子，其表达已通过将密码子改变为最少常用的哺乳动物密码子以及具有用于在高转录活性启动子和高度稳定的聚腺苷酸化信号之间引入外源基因的克隆位点的基因盒。

8. 发明申请

US20130155030A1 DISPLAY SYSTEM AND DETECTION METHOD 审中-公开
标题翻译：显示系统和检测方法
公开(公告)号：US20130155030A1
公开(公告)日：2013-06-20
申请号：US13820584
申请日：2011-07-13
申请人： Michihiro Kawai , Keiichi Yamamoto
发明人： Michihiro Kawai , Keiichi Yamamoto
IPC分类号： G06F3/042
CPC分类号： G06F3/042 , G06F3/0428
摘要： A display system displays objects in a display region in a manner arranged in a predetermined orientation. One light-emitting element of a sensor array emits light to the objects in the predetermined orientation. The display system prestores data which associates numerical value ranges different from each other with the objects, respectively. When light reflected by a finger is received by light-receiving elements of the sensor array, the display system calculates the number of the light-receiving elements that have received the reflected light, identifies one object associated with the numerical value range including the calculated number of the light-receiving elements, from among the objects, based on the calculated number of the light-receiving elements and the stored data, and performs processing corresponding to the identified object.
摘要翻译：显示系统以预定方向布置的方式在显示区域中显示对象。传感器阵列的一个发光元件以预定取向向对象发光。显示系统预先分别将数据值彼此不同的数据与对象相关联。当由手指反射的光被传感器阵列的光接收元件接收时，显示系统计算已经接收到反射光的光接收元件的数量，识别与包括计算出的数字的数值范围相关联的一个对象的光接收元件，基于计算出的光接收元件数量和存储的数据，并且执行与所识别的对象相对应的处理。

9. 发明授权

US08456854B2 Method of repair of electronic device and repair system 失效
公开(公告)号：US08456854B2
公开(公告)日：2013-06-04
申请号：US12285632
申请日：2008-10-09
申请人： Shigeo Iriguchi , Kiyoyuki Hatanaka , Satoshi Watanabe , Nobuo Taketomi , Keiichi Yamamoto , Masaru Sugie
发明人： Shigeo Iriguchi , Kiyoyuki Hatanaka , Satoshi Watanabe , Nobuo Taketomi , Keiichi Yamamoto , Masaru Sugie
IPC分类号： H05K7/02 , H05K7/06 , H05K7/08 , H05K7/10
CPC分类号： H05K3/3494 , H05K1/0212 , H05K3/225 , H05K2203/101 , H05K2203/176 , Y10T29/49137
摘要： A repair system which prevents heating of weakly heat resistant devices together and causing deterioration of the quality when preheating a first surface of the circuit board, wherein an electromagnetic induction material is buried in advance inside the circuit board near a specific electronic device envisioned as needed repair when becoming a defective electronic device in a production process and an electromagnetic coil emitting electromagnetic waves to an electromagnetic induction member in the vicinity of the repair device is provided and the heat generated by the electromagnetic induction member due to the electromagnetic waves enables the repair device to be heated and detached from the circuit board.

10. 发明授权

US08278794B2 Axial gap type motor and method of manufacturing rotor of motor 有权
标题翻译：轴向间隙式马达及其制造方法
公开(公告)号：US08278794B2
公开(公告)日：2012-10-02
申请号：US12918638
申请日：2009-10-29
申请人： Satoshi Ishikawa , Keiichi Yamamoto , Shoei Abe
发明人： Satoshi Ishikawa , Keiichi Yamamoto , Shoei Abe
IPC分类号： H02K1/27
CPC分类号： H02K1/30 , H02K1/2793 , H02K15/02 , H02K15/03 , H02K21/24 , Y10T29/49012
摘要： The rotor 11 of an axial gap type motor 10 is provided with a plurality of main magnets 41 respectively magnetized in an axial direction of a rotational axis and disposed at predetermined intervals in a peripheral direction, a plurality of yokes 42 structured by a laminated member 71 produced by winding a tape-shaped electromagnetic steel plate 60 and respectively disposed on both sides of the main magnets 41 in the axial direction, and a rotor frame 30 made of a die-cast alloy and including a plurality of ribs 31 respectively interposed between the main magnets 41 adjoining each other in the peripheral direction and extending in the radial direction, and an inner cylindrical portion 32 and an outer cylindrical portion 33 respectively formed on the radially inner side of the ribs 31 and on the radially outer side of the ribs 31. According to this structure, the yokes structured by the wound laminated member and the rotor frame can be firmly unified with each other, thereby being able to secure such rigidity that can withstand a centrifugal force generated due to the rotation of the rotor and a magnetic suction force given from the stator.
摘要翻译：轴向间隙型电动机10的转子11具有分别沿旋转轴的轴向磁化并沿周向以规定间隔设置的多个主磁体41，由层叠部件71构成的多个磁轭42 通过缠绕分别设置在主磁体41的轴向两侧的带状电磁钢板60和由压铸合金制成的转子架30制成，转子架30分别插入在压铸合金中主磁体41在圆周方向上彼此邻接并沿径向延伸，以及分别形成在肋31的径向内侧上和肋31的径向外侧上的内圆柱形部分32和外圆柱形部分33 根据该结构，由缠绕层叠构件和转子架构成的轭可以彼此牢固地一体化，从而能够 o确保能够承受由于转子的旋转产生的离心力和从定子给出的磁吸力的刚性。

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