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1. 发明申请

US20120247750A1 SERVER DEVICE, CONTROL DEVICE, SERVER RACK, RECORDING MEDIUM STORING COOLING CONTROL PROGRAM, AND COOLING CONTROL METHOD 审中-公开
标题翻译：服务器设备，控制设备，服务器机架，记录存储冷却控制程序和冷却控制方法
公开(公告)号：US20120247750A1
公开(公告)日：2012-10-04
申请号：US13352601
申请日：2012-01-18
申请人： Hiroki Kobayashi , Yuichi Sato , Takahiro Kimura , Jun Taniguchi , Seiji Hibino , Toshio Sugimoto , Yasushi Umezawa , Reiko Kondo , Bernhard Schräder , Gerold Scheidler , Van Son Nguyen , Geoff Poskitt
发明人： Hiroki Kobayashi , Yuichi Sato , Takahiro Kimura , Jun Taniguchi , Seiji Hibino , Toshio Sugimoto , Yasushi Umezawa , Reiko Kondo , Bernhard Schräder , Gerold Scheidler , Van Son Nguyen , Geoff Poskitt
IPC分类号： H05K5/02 , G05D23/00
CPC分类号： H05K7/20836
摘要： A server device includes: electronic devices; a housing that houses the electronic devices; at least one fan; air volume control units configured to adjust a volume of cooling airflow which is generated by rotation of the at least one fan and is ventilated through the electronic devices by opening and closing of respective valves; a valve opening control unit configured to control valve opening degrees of the air volume control units so that temperatures inside the electronic devices become a given target temperature; a fan control unit configured to run the at least one fan at a fan rotating speed that achieves a volume of cooling airflow to make temperatures inside the electronic devices become the given target temperature at a valve opening degree higher than the valve opening degrees that the valve opening control unit controls.
摘要翻译：服务器设备包括：电子设备; 容纳电子设备的房屋; 至少有一个风扇; 空气量控制单元，被配置为调节通过所述至少一个风扇的旋转产生的冷却气流的体积，并且通过打开和关闭各个阀通过电子设备通风; 阀开度控制单元，被配置为控制所述空气量控制单元的阀开度，使得所述电子设备内的温度变为给定的目标温度; 风扇控制单元，其构造成以实现一定体积的冷却气流的风扇转速运行所述至少一个风扇，以使电子设备内部的温度变得高于阀开度高于阀开度的给定目标温度，开启控制单元控制。

2. 发明授权

US08719361B2 Relay device, MAC address search method 有权
标题翻译：中继设备，MAC地址搜索方式
公开(公告)号：US08719361B2
公开(公告)日：2014-05-06
申请号：US12855246
申请日：2010-08-12
申请人： Yasushi Umezawa , Takeshi Shimizu , Takashi Miyoshi
发明人： Yasushi Umezawa , Takeshi Shimizu , Takashi Miyoshi
IPC分类号： G06F15/167
CPC分类号： H04L45/00 , H04L12/12 , H04L45/54 , H04L49/90 , Y02D50/40 , Y02D50/42
摘要： A relay device includes: memories, each memory being operable to store at least a data pair formed of a MAC address and a port number; a search unit to search only amongst ones of the memories having valid data pairs when searching for a port number based upon a MAC address; a data moving unit to move valid data pairs to different locations within the plurality of memories in order to reduce a total number of memories, amongst the plurality thereof, having valid data pairs; and a power supply controller to selectively stop supplying power to ones of the memories storing only invalid data.
摘要翻译：中继装置包括：存储器，每个存储器可操作以至少存储由MAC地址和端口号形成的数据对; 搜索单元，用于在基于MAC地址搜索端口号时仅搜索具有有效数据对的存储器中的一个; 数据移动单元，用于将有效数据对移动到所述多个存储器内的不同位置，以便减少其多个存储器中具有有效数据对的存储器总数; 以及电源控制器，用于选择性地停止向仅存储无效数据的存储器供电。

3. 发明授权

US08276108B2 Circuit design apparatus and circuit design method 失效
标题翻译：电路设计及电路设计方法
公开(公告)号：US08276108B2
公开(公告)日：2012-09-25
申请号：US12491030
申请日：2009-06-24
申请人： Yasushi Umezawa , Takeshi Shimizu
发明人： Yasushi Umezawa , Takeshi Shimizu
IPC分类号： G06F9/455
CPC分类号： G06F17/505
摘要： A circuit design apparatus for designing an LSI including a memory circuit for storing data and an error protection circuit for performing an error protection over the data stored in the memory circuit on the basis of design information, the circuit design apparatus includes: an extracting unit for extracting information of configuration of the memory circuit with error protection circuit from the design information; and a circuit arrangement controller for determining whether to insert a check circuit for supplying a check signal into the memory circuit to verify the error protection circuit on the configuration information.
摘要翻译：一种电路设计装置，用于设计包括用于存储数据的存储电路的LSI和用于基于设计信息对存储在存储电路中的数据执行错误保护的错误保护电路，电路设计装置包括：提取单元，从设计信息中提取具有错误保护电路的存储器电路的配置信息; 以及电路布置控制器，用于确定是否将用于提供检查信号的检查电路插入到存储器电路中，以便在配置信息上验证错误保护电路。

4. 发明授权

US07315895B2 Fault containment and error handling in a partitioned system with shared resources 有权
公开(公告)号：US07315895B2
公开(公告)日：2008-01-01
申请号：US10150618
申请日：2002-05-17
申请人： Kazunori Masuyama , Yasushi Umezawa , Jeremy J. Farrell , Sudheer Miryala , Takeshi Shimizu , Hitoshi Oi , Patrick N. Conway
发明人： Kazunori Masuyama , Yasushi Umezawa , Jeremy J. Farrell , Sudheer Miryala , Takeshi Shimizu , Hitoshi Oi , Patrick N. Conway
IPC分类号： G06F15/173 , G06F15/00 , G06F11/00
摘要： A system and method for fault containment and error handling within a domain in a partitioned computer system includes a system manager having read and write access to a resource definition table. The system manager is adapted to quiesce the system when failure occurs within a domain, identify an allocated resource associated with the failed domain, identify a non-failed domain, and exit the quiesce mode for the non-failed domain, thereby containing a failure within the failed domain. The system manager further handles an error within the failed domain by deallocating a resource allocated to the failed domain so that the resource becomes available to non-failed domains.

5. 发明授权

US06490630B1 System and method for avoiding deadlock in multi-node network 有权
标题翻译：避免多节点网络死锁的系统和方法
公开(公告)号：US06490630B1
公开(公告)日：2002-12-03
申请号：US09285316
申请日：1999-04-02
申请人： Wing Leong Poon , Patrick J. Helland , Takeshi Shimizu , Yasushi Umezawa , Wolf-Dietrich Weber
发明人： Wing Leong Poon , Patrick J. Helland , Takeshi Shimizu , Yasushi Umezawa , Wolf-Dietrich Weber
IPC分类号： G06F1516
CPC分类号： G06F15/17
摘要： A computer architecture for avoiding a deadlock condition in an interconnection network comprises a messaging buffer having a size pre-calculated to temporarily store outgoing messages from a node. Messages are classified according to their service requirements and messaging protocols, and reserved quotas in the messaging buffer are allocated for different types of messages. The allocations of the reserved quotas are controlled by a mechanism that, to prevent overflow, limits the maximum number of messages that can be outstanding at any time. The messaging buffer is sized large enough to guarantee that a node is always able to service incoming messages, thereby avoiding deadlock and facilitating forward progress in communications. The buffer may be bypassed to improve system performance when the buffer is empty or when data in the buffer is corrupted. In addition, a multicast engine facilitates dense packing of the buffer and derives information from a message header to determine whether there is a multicast to perform and to permit passage of messages. Other considerations to reduce the buffer size are incorporated.
摘要翻译：用于避免互连网络中的死锁状况的计算机体系结构包括具有预先计算以便临时存储来自节点的传出消息的大小的消息传送缓冲器。消息根据其服务要求和消息协议进行分类，消息缓冲区中的保留配额被分配给不同类型的消息。保留配额的分配由一种机制来控制，为了防止溢出，可以限制任何时候可以发送的最大消息数。消息传递缓冲区的大小足够大，以确保节点始终能够服务传入的消息，从而避免死锁并促进通信的前进进程。当缓冲区为空或缓冲区中的数据被破坏时，可能会旁路缓冲区以提高系统性能。此外，多播引擎促进了缓冲器的密集打包，并从消息头部导出信息，以确定是否存在要执行的多播并允许消息通过。纳入了减少缓冲区大小的其他考虑因素。

6. 发明授权

US08966140B2 Data transfer apparatus and data transfer method 有权
标题翻译：数据传输装置和数据传输方法
公开(公告)号：US08966140B2
公开(公告)日：2015-02-24
申请号：US13115982
申请日：2011-05-25
申请人： Yasushi Umezawa
发明人： Yasushi Umezawa
IPC分类号： G06F13/12 , G08C15/00 , H04L12/801 , H04L12/861
CPC分类号： H04L47/12 , H04L49/90
摘要： A data transfer apparatus includes a plurality of input ports, a plurality of output ports and a switch unit between the plurality of input ports and the plurality of output ports. Each input port includes an input buffer configured to store input data including destination information indicating destinations of respective pieces of the input data, a first buffer monitoring unit configured to monitor a first usage rate of the input buffer, and a first frequency control unit configured to control a first operating frequency of the input buffer on the basis of the first usage rate. Each output port includes an output buffer configured to store output data, a second buffer monitoring unit configured to monitor a second usage rate of the output buffer, and a second frequency control unit configured to control a second operating frequency of the output buffer on the basis of the second usage rate.
摘要翻译：数据传送装置包括多个输入端口，多个输出端口和多个输入端口与多个输出端口之间的开关单元。每个输入端口包括：输入缓冲器，被配置为存储包括指示各段输入数据的目的地的目的地信息的输入数据;第一缓冲器监视单元，被配置为监视输入缓冲器的第一使用率;以及第一频率控制单元，基于第一使用率控制输入缓冲器的第一工作频率。每个输出端口包括被配置为存储输出数据的输出缓冲器，被配置为监视输出缓冲器的第二使用率的第二缓冲器监视单元和被配置为基于该输出缓冲器的第二操作频率来控制输出缓冲器的第二操作频率的第二频率控制单元的第二使用率。

7. 发明授权

US08392733B2 Network apparatus 有权
标题翻译：网络设备
公开(公告)号：US08392733B2
公开(公告)日：2013-03-05
申请号：US12647237
申请日：2009-12-24
申请人： Yasushi Umezawa
发明人： Yasushi Umezawa
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/325 , G06F1/3253 , H04L49/101 , H04L49/90 , H04Q3/0004 , H04Q3/52 , Y02D10/126 , Y02D10/128 , Y02D10/151
摘要： An apparatus includes a switching unit to output data input from an input unit to an output unit to which the data is to be output, and an input control unit, wherein input units included in a same group among a plurality of input units each have a buffer to store data received from another apparatus; a multiplexer connected to the buffer and to a buffer in another input unit in the same group, and capable of selectively outputting data; and an input data processing portion connected to the multiplexer and performing specific input data processing on data input from the multiplexer and outputting data after the specific input data processing to the switching unit, wherein the input control unit controls a data output selection of the multiplexer and controls supply of power or supply of a clock signal to the multiplexer and the input data processing portion.
摘要翻译：一种装置，包括：切换单元，用于将从输入单元输入的数据输出到要输出数据的输出单元;以及输入控制单元，其中包括在多个输入单元中的相同组中的输入单元各自具有用于存储从另一设备接收的数据的缓冲器; 连接到缓冲器的多路复用器和同一组中的另一个输入单元中的缓冲器，并且能够选择性地输出数据; 以及输入数据处理部分，连接到所述多路复用器，并对从所述多路复用器输入的数据执行特定的输入数据处理，并且在所述特定输入数据处理之后向所述切换单元输出数据，其中所述输入控制单元控制所述多路复用器控制向多路复用器和输入数据处理部分供电或提供时钟信号。

8. 发明申请

US20100005433A1 CIRCUIT DESIGN APPARATUS AND CIRCUIT DESIGN METHOD 失效
标题翻译：电路设计和电路设计方法
公开(公告)号：US20100005433A1
公开(公告)日：2010-01-07
申请号：US12491030
申请日：2009-06-24
申请人： Yasushi Umezawa , Takeshi Shimizu
发明人： Yasushi Umezawa , Takeshi Shimizu
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A circuit design apparatus for designing an LSI including a memory circuit for storing data and an error protection circuit for performing an error protection over the data stored in the memory circuit on the basis of design information, the circuit design apparatus includes: an extracting unit for extracting information of configuration of the memory circuit with error protection circuit from the design information; and a circuit arrangement controller for determining whether to insert a check circuit for supplying a check signal into the memory circuit to verify the error protection circuit on the configuration information.
摘要翻译：一种电路设计装置，用于设计包括用于存储数据的存储电路的LSI和用于基于设计信息对存储在存储电路中的数据执行错误保护的错误保护电路，电路设计装置包括：提取单元，从设计信息中提取具有错误保护电路的存储器电路的配置信息; 以及电路布置控制器，用于确定是否将用于提供检查信号的检查电路插入到存储器电路中，以便在配置信息上验证错误保护电路。

9. 发明授权

US07380001B2 Fault containment and error handling in a partitioned system with shared resources 有权
标题翻译：具有共享资源的分区系统中的故障控制和错误处理
公开(公告)号：US07380001B2
公开(公告)日：2008-05-27
申请号：US10150618
申请日：2002-05-17
申请人： Kazunori Masuyama , Yasushi Umezawa , Jeremy J. Farrell , Sudheer Miryala , Takeshi Shimizu , Hitoshi Oi , Patrick N. Conway
发明人： Kazunori Masuyama , Yasushi Umezawa , Jeremy J. Farrell , Sudheer Miryala , Takeshi Shimizu , Hitoshi Oi , Patrick N. Conway
IPC分类号： G06F15/173 , G06F15/00 , G06F11/00
CPC分类号： H04L41/12 , H04L41/0654 , H04L43/0817
摘要： A system and method for fault containment and error handling within a domain in a partitioned computer system includes a system manager having read and write access to a resource definition table. The system manager is adapted to quiesce the system when failure occurs within a domain, identify an allocated resource associated with the failed domain, identify a non-failed domain, and exit the quiesce mode for the non-failed domain, thereby containing a failure within the failed domain. The system manager further handles an error within the failed domain by deallocating a resource allocated to the failed domain so that the resource becomes available to non-failed domains.
摘要翻译：在分区计算机系统中的域内的用于故障容纳和错误处理的系统和方法包括具有对资源定义表的读取和写入访问的系统管理器。系统管理器适用于在域内发生故障时停止系统，识别与故障域相关联的分配资源，识别非故障域，并退出非故障域的静默模式，从而在失败的域。系统管理员通过取消分配给故障域的资源来进一步处理故障域内的错误，以使资源变得可用于非故障域。

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