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1. 发明授权

US07295604B2 Method for determining jitter of a signal in a serial link and high speed serial link 有权
标题翻译：用于确定串行链路和高速串行链路中的信号抖动的方法
公开(公告)号：US07295604B2
公开(公告)日：2007-11-13
申请号：US10720974
申请日：2003-11-24
申请人： Hayden C. Cranford, Jr. , Marcel A. Kossel , Vernon R. Norman , Martin L. Schmatz
发明人： Hayden C. Cranford, Jr. , Marcel A. Kossel , Vernon R. Norman , Martin L. Schmatz
IPC分类号： H04B3/46
CPC分类号： H04L25/068 , H04B3/462 , H04L1/205
摘要： The method for determining jitter of a signal in a serial link according to the invention comprising the following steps: First, a section of the signal transmitted via a transmission channel is sampled at different sampling times. The total number of edges in the section is determined. The neighboring sample values are analyzed and from that a statistical value is formed. From the statistical value and the total number of edges a figure of merit is determined. Finally, by means of a look-up table or a jitter-versus-figure of merit curve, the total jitter corresponding to the figure of merit is derived.
摘要翻译：根据本发明的用于确定串行链路中的信号的抖动的方法包括以下步骤：首先，经由传输信道发送的信号的一部分在不同的采样时间被采样。确定该部分中的边缘总数。分析相邻的样本值，并从中形成统计值。从统计值和边缘总数确定品质因数。最后，通过查询表或优点曲线的抖动对数值，推导出与品质因数对应的总抖动。

2. 发明授权

US07512177B2 Method and apparatus for generating random jitter 失效
标题翻译：用于产生随机抖动的方法和装置
公开(公告)号：US07512177B2
公开(公告)日：2009-03-31
申请号：US11828390
申请日：2007-07-26
申请人： Hayden C. Cranford, Jr. , Marcel A. Kossel , Vernon R. Norman , Martin L. Schmatz
发明人： Hayden C. Cranford, Jr. , Marcel A. Kossel , Vernon R. Norman , Martin L. Schmatz
IPC分类号： H04B3/46
CPC分类号： H04L25/068 , H04B3/462 , H04L1/205
摘要： Apparatuses and methods comprise a phase shifter, an adjustable capacitance configured to adjust a phase shift of said phase shifter, an arbitrary waveform generator configured to adjust the adjustable capacitance, and a pulse pattern generator coupled to the phase shifter, the phase shifter is configured to control the pulse pattern generator. In one aspect, an adjustable capacitance is at least one varactor diode. In another, a pair of varactor diodes are separated by λ/4 lines, an input and an output of the adjustable capacitance is AC-coupled, and the arbitrary waveform generator is configured to adjust the adjustable capacitance through a gaussian noise signal input to the pair of varactor diodes. A deterministic jitter generator may be coupled to the pulse pattern generator. An open-circuited stub line may be input to the pattern generator, a deterministic jitter content number adjustable varying stub line length.
摘要翻译：装置和方法包括移相器，被配置为调整所述移相器的相移的可调电容，被配置为调节可调电容的任意波形发生器以及耦合到移相器的脉冲图形发生器，所述移相器被配置为控制脉冲模式发生器。在一个方面，可调电容是至少一个变容二极管。另一方面，一对变容二极管由λ/ 4线分开，可调电容的输入和输出是交流耦合的，并且任意波形发生器被配置成通过高斯噪声信号输入到一对变容二极管。确定性抖动发生器可以耦合到脉冲图案发生器。可以向模式发生器输入开路短线，确定性抖动内容数可调，可变长短线长度。

3. 发明申请

US20080150599A1 METHOD AND APPARATUS FOR GENERATING RANDOM JITTER 失效
标题翻译：用于生成随机抖动器的方法和装置
公开(公告)号：US20080150599A1
公开(公告)日：2008-06-26
申请号：US11828390
申请日：2007-07-26
申请人： Hayden C. Cranford , Marcel A. Kossel , Vernon R. Norman , Martin L. Schmatz
发明人： Hayden C. Cranford , Marcel A. Kossel , Vernon R. Norman , Martin L. Schmatz
IPC分类号： H03K3/84
CPC分类号： H04L25/068 , H04B3/462 , H04L1/205
摘要： Apparatuses and methods comprise a phase shifter, an adjustable capacitance configured to adjust a phase shift of said phase shifter, an arbitrary waveform generator configured to adjust the adjustable capacitance, and a pulse pattern generator coupled to the phase shifter, the phase shifter is configured to control the pulse pattern generator. In one aspect, an adjustable capacitance is at least one varactor diode. In another, a pair of varactor diodes are separated by λ/4 lines, an input and an output of the adjustable capacitance is AC-coupled, and the arbitrary waveform generator is configured to adjust the adjustable capacitance through a gaussian noise signal input to the pair of varactor diodes. A deterministic jitter generator may be coupled to the pulse pattern generator. An open-circuited stub line may be input to the pattern generator, a deterministic jitter content number adjustable varying stub line length.
摘要翻译：装置和方法包括移相器，被配置为调整所述移相器的相移的可调电容，被配置为调节可调电容的任意波形发生器以及耦合到移相器的脉冲图形发生器，所述移相器被配置为控制脉冲模式发生器。在一个方面，可调电容是至少一个变容二极管。另一方面，一对变容二极管由λ/ 4线分开，可调电容的输入和输出是交流耦合的，并且任意波形发生器被配置成通过高斯噪声信号输入到一对变容二极管。确定性抖动发生器可以耦合到脉冲图案发生器。可以向模式发生器输入开路短线，确定性抖动内容数可调，可变长短线长度。

4. 发明授权

US07809054B2 One-sample-per-bit decision feedback equalizer (DFE) clock and data recovery 失效
标题翻译：单采样每位决策反馈均衡器（DFE）时钟和数据恢复
公开(公告)号：US07809054B2
公开(公告)日：2010-10-05
申请号：US11405997
申请日：2006-04-18
申请人： Juan A. Carballo , Hayden C. Cranford, Jr. , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
发明人： Juan A. Carballo , Hayden C. Cranford, Jr. , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03063
摘要： Disclosed are a receiver circuit, method and design architecture of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER). An integrating receiver is combined with a decision feedback equalizer along with the appropriate (CDR) loop phase detector to maintain a single sample per bit requirement. The incoming voltage is converted to a current and connected to a current summing node. Weighted currents determined by the values of previously detected bits and their respective feedback coefficients are also connected to this node. Additionally, the summed currents is integrated and converted to a voltage. A sampler is utilized to make a bit decision based on the resulting voltage. After sampling, the integrator is reset before analysis of the next bit. The necessary amplification is achieved by maximizing the sensitivity of the latch, using integration in front of the data latch.
摘要翻译：公开了一种在接收机中利用/产生一个每位采样的判决反馈均衡器（DFE）时钟和数据恢复（CDR）架构的接收器电路，方法和设计架构，并且降低了误码率（BER ）。集成接收机与决策反馈均衡器以及适当的（CDR）环路相位检测器相结合，以保持每位需求的单个采样。输入电压被转换为电流并连接到电流求和节点。由先前检测到的位及其各自的反馈系数的值确定的加权电流也连接到该节点。另外，总和电流被积分并转换成电压。采样器用于基于所得到的电压进行位决定。采样后，积分器在分析下一位之前被复位。通过使用在数据锁存器前面的积分来最大化锁存器的灵敏度来实现必要的放大。

5. 发明授权

US07661052B2 Using statistical signatures for testing high-speed circuits 失效
标题翻译：使用统计特征来测试高速电路
公开(公告)号：US07661052B2
公开(公告)日：2010-02-09
申请号：US12021950
申请日：2008-01-29
申请人： Hayden C. Cranford, Jr. , Vernon R. Norman , Martin L. Schmatz
发明人： Hayden C. Cranford, Jr. , Vernon R. Norman , Martin L. Schmatz
IPC分类号： G06F11/277 , G06F11/16
CPC分类号： G01R31/31901 , G01R31/31707
摘要： A method and system for testing a high-speed circuit is disclosed. The method and system include obtaining a high-speed statistical signature of the high-speed circuit using a conventional tester. The method and system further include comparing the high-speed statistical signature of the high-speed circuit to an expected signature. Consequently, it can be determined whether the high-speed circuit functions within the desired parameters.
摘要翻译：公开了一种用于测试高速电路的方法和系统。该方法和系统包括使用常规测试仪获得高速电路的高速统计特征。该方法和系统还包括将高速电路的高速统计签名与预期签名进行比较。因此，可以确定高速电路是否在期望的参数内起作用。

6. 发明授权

US07477713B2 method for providing automatic adaptation to frequency offsets in high speed serial links 有权
标题翻译：用于在高速串行链路中提供自动适应频率偏移的方法
公开(公告)号：US07477713B2
公开(公告)日：2009-01-13
申请号：US10791175
申请日：2004-03-02
申请人： Hayden C. Cranford, Jr. , Gareth John Nicholls , Bobak Modaress-Razavi , Vernon R. Norman , Martin L. Schmatz
发明人： Hayden C. Cranford, Jr. , Gareth John Nicholls , Bobak Modaress-Razavi , Vernon R. Norman , Martin L. Schmatz
IPC分类号： H04L7/02
CPC分类号： H03L7/0814 , H03L7/07 , H04L2027/0065 , H04L2027/0067
摘要： Aspects of providing automatic adaptation to frequency offsets in high speed serial links are described. First signals for phase adjusts in a receiver link are adjusted by detecting trends in the first signals to generate second signals, the second signals improving a rate of compensation for the frequency offsets by the phase adjusts. An up/down counter is included for counting signals for phase adjustments by a clock-data-recovery loop of a serial receiver. An adder is coupled to the up/down counter and outputs accumulated data indicative of a trend in the phase adjustments. Combinatorial logic coupled to the adder adapts the signals based on the accumulated data.
摘要翻译：描述了在高速串行链路中提供对频偏的自动适配的方面。通过检测第一信号中的趋势来产生第二信号来调整在接收机链路中进行相位调整的第一信号，第二信号通过相位调整来提高对频偏的补偿率。包括一个向上/向下计数器，用于通过串行接收器的时钟数据恢复环来对信号进行相位调整。加法器耦合到上/下计数器并输出指示相位调整趋势的累加数据。耦合到加法器的组合逻辑基于累积数据来适配信号。

7. 发明授权

US07349498B2 Method and system for data and edge detection with correlation tables 有权
标题翻译：具有相关表的数据和边缘检测方法和系统
公开(公告)号：US07349498B2
公开(公告)日：2008-03-25
申请号：US10265981
申请日：2002-10-07
申请人： Hayden C Cranford, Jr. , Vernon R. Norman , Martin L. Schmatz
发明人： Hayden C Cranford, Jr. , Vernon R. Norman , Martin L. Schmatz
IPC分类号： H04L27/06 , H03D27/06
CPC分类号： H04L7/0338 , H03K5/1534
摘要： A system and method is disclosed for evaluating a data group of oversampled bits to detect edge transitions and for improving use of information available from a sampled data while maintaining acceptable noise rejection. An edge detection system for receiving a serial data stream includes a sampler for collecting a sample pattern from the serial data stream, the sample pattern including a succession of a plurality of data samples from the data stream with the plurality of data samples including multiple samples during a bit time associated with the data stream; a memory, coupled to the sampler, for storing one or more successive sample patterns; and a correlator, coupled to the memory, for producing a sample condition signal using a set of predefined patterns by comparing the stored sampled patterns to the predefined patterns.
摘要翻译：公开了一种系统和方法，用于评估过采样比特的数据组以检测边缘转换并改善对采样数据可用信息的使用，同时保持可接受的噪声抑制。用于接收串行数据流的边缘检测系统包括：采样器，用于从串行数据流收集采样模式，样本模式包括来自数据流的多个数据样本的一系列，其中多个数据样本包括多个样本与数据流相关联的一段时间; 耦合到采样器的存储器，用于存储一个或多个连续的采样图案; 以及耦合到存储器的相关器，用于通过将所存储的采样图案与预定义图案进行比较，使用一组预定义图案来产生采样条件信号。

8. 发明授权

US07340660B2 Method and system for using statistical signatures for testing high-speed circuits 有权
标题翻译：统计特征用于测试高速电路的方法和系统
公开(公告)号：US07340660B2
公开(公告)日：2008-03-04
申请号：US10680679
申请日：2003-10-07
申请人： Hayden C. Cranford, Jr. , Vernon R. Norman , Martin L. Schmatz
发明人： Hayden C. Cranford, Jr. , Vernon R. Norman , Martin L. Schmatz
IPC分类号： G01R31/3193 , G01R31/316
CPC分类号： G01R31/31901 , G01R31/31707
摘要： A method and system for testing a high-speed circuit is disclosed. The method and system include obtaining a high-speed statistical signature of the high-speed circuit using a conventional tester. The method and system further include comparing the high-speed statistical signature of the high-speed circuit to an expected signature. Consequently, it can be determined whether the high-speed circuit functions within the desired parameters.
摘要翻译：公开了一种用于测试高速电路的方法和系统。该方法和系统包括使用常规测试仪获得高速电路的高速统计特征。该方法和系统还包括将高速电路的高速统计签名与预期签名进行比较。因此，可以确定高速电路是否在期望的参数内起作用。

9. 发明申请

US20080240224A1 STRUCTURE FOR ONE-SAMPLE-PER-BIT DECISION FEEDBACK EQUALIZER (DFE) CLOCK AND DATA RECOVERY 审中-公开
标题翻译：一次性决策反馈均衡器（DFE）时钟和数据恢复的结构
公开(公告)号：US20080240224A1
公开(公告)日：2008-10-02
申请号：US12138214
申请日：2008-06-12
申请人： JUAN A. CARBALLO , Hayden C. Cranford , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
发明人： JUAN A. CARBALLO , Hayden C. Cranford , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
IPC分类号： H04L27/01
CPC分类号： H04L25/03885 , H04L25/03057 , H04L2025/03356
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER) is provided. The design generally includes a receiver circuit. The receiver circuit generally includes a decision feedback equalizer (DFE) that produces one sample per bit, and means for automatically self-adjusting the DFE to enable an eye centering process by which peak energy is maintained within the receiver circuit when phase error is a minimum.
摘要翻译：一种体现在机器可读存储介质中的设计结构，用于设计，制造和/或测试利用/产生一个每位采样的判决反馈均衡器（DFE）时钟和数据恢复（CDR）架构的设计提供接收机并降低误码率（BER）。该设计通常包括接收器电路。接收器电路通常包括每位产生一个采样的判决反馈均衡器（DFE），以及用于自动自调整DFE的装置，以便当相位误差最小时能够在接收器电路内保持峰值能量的眼睛对中过程。

10. 发明申请

US20080133164A1 USING STATISTICAL SIGNATURES FOR TESTING HIGH-SPEED CIRCUITS 失效
标题翻译：使用统计信号测试高速电路
公开(公告)号：US20080133164A1
公开(公告)日：2008-06-05
申请号：US12021950
申请日：2008-01-29
申请人： Hayden C. Cranford , Vernon R. Norman , Martin L. Schmatz
发明人： Hayden C. Cranford , Vernon R. Norman , Martin L. Schmatz
IPC分类号： G01R31/00 , G06F19/00
CPC分类号： G01R31/31901 , G01R31/31707
摘要： A method and system for testing a high-speed circuit is disclosed. The method and system include obtaining a high-speed statistical signature of the high-speed circuit using a conventional tester. The method and system further include comparing the high-speed statistical signature of the high-speed circuit to an expected signature. Consequently, it can be determined whether the high-speed circuit functions within the desired parameters.
摘要翻译：公开了一种用于测试高速电路的方法和系统。该方法和系统包括使用常规测试仪获得高速电路的高速统计特征。该方法和系统还包括将高速电路的高速统计签名与预期签名进行比较。因此，可以确定高速电路是否在期望的参数内起作用。

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