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1. 发明专利

JPS622714A SYNCHRONOUS SEQUENCE CIRCUIT 失效
公开(公告)号：JPS622714A
公开(公告)日：1987-01-08
申请号：JP14039085
申请日：1985-06-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KIUCHI ATSUSHI , KANEKO KENJI , ISHIDA JUN , NAKAGAWA TETSUYA , SATOU TOMORU , HAGIWARA YOSHIMUNE
IPC分类号： H03K3/037 , H03K3/356
摘要： PURPOSE:To obtain a stable synchronous sequence circuit having high resistance to the hazard by giving a shift between a fetching time point of the input signal and a fixing time point of the output signal. CONSTITUTION:The logic circuits 102 and 104 form a holding circuit and a delay circuit 103 functions to produce a shift between a holding time point of the holding circuit and a fetching time point of an input signal. A synchronizing clock CLK1 decides the fetching time point of the input signal and a synchronizing clock CLK2 fixes the output signal and actuates the holding circuit. Both input signals S and R are not fixed yet before a time point 201 when the signal CLK1 is enable and the transition starts concurrently with the time point 201 of a synchronizing period. Even in such a case, the output signal Qn is fixed with the correct value as long as the transition is through and stable during a period 204. Thus the output signal Qn (or Qn) is fixed with the correct value even though an unstable state shown by 206 is caused immediately after synchronization. Then this synchronizing sequence circuit has no malfunction unlike a conventional case.

2. 发明专利

JPS62146008A SELECTING CIRCUIT 失效
公开(公告)号：JPS62146008A
公开(公告)日：1987-06-30
申请号：JP28819585
申请日：1985-12-20
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , HITACHI VLSI ENG
发明人： KIUCHI ATSUSHI , ISHIDA JUN , KANEKO KENJI , NAKAGAWA TETSUYA , SATOU TOMORU , MASUMURA SHIGEKI , SUZUKI NORIYASU , HAGIWARA YOSHIMUNE
IPC分类号： H03K17/00 , H03K17/693
摘要： PURPOSE:To make a quick operation possible by selecting one signal in each period from (n-1)-number of input signals taken in from the external and one input signal, which is obtained by feeding back the output of the preceding period, to make it unnecessary to set the time when a decoding signal for control is settled. CONSTITUTION:(n-1)-Number of input signals out of n-number of input signals to be selected are input signals from the external, and remainder one is the signal obtained by feeding back the output of a selecting circuit 409 or a logic circuit 406 following the circuit 409. These n-number of input signals are controlled by a control signal C410 for selection. If any of (n-1)-number of external input signals is not selected, the control signal C410 selects certainly the feedback signal of the state in the preceding period. This feedback signal is selected then to eliminate the no-selection mode, and thereby, the output of the selecting circuit 409 is certainly outputted in each period. Thus, a preceding erroneous selecting signal is cancelled immediately with a correct selecting signal even if the erroneous signal is temporarily selected in the initials stage of synchronization.

3. 发明专利

JPS62224852A DIGITAL SIGNAL PROCESSOR 失效
公开(公告)号：JPS62224852A
公开(公告)日：1987-10-02
申请号：JP6566686
申请日：1986-03-26
申请人： HITACHI LTD
发明人： SATOU TOMORU
IPC分类号： G11C29/00 , G06F15/78 , G11C29/02 , G11C29/56
摘要： PURPOSE:To accurately test the operation of a data RAM by connecting to an output register one of or both of the X, Y-bus to supply the read data from a data RAM to an arithmetic operation circuit, etc. CONSTITUTION:In case of an operation of reading from the data RAM, after the setting of the page and the address of the data RAM from which the data is read out to an X-pointer XP and a RAM-pointer RPA or an RPB, function signals F0-F3 are inputted to make a read/write signal R/W in a high level, and further, after the designating of a read action, a chip selecting signal CS is made in low level. Accordingly, the data in a specified address of the data RAM is read out, transferred through the X-bus, and outputted to data signal lines D0-D15 via a multiplexer MPX and an output register OR. In such a way, the operation test of the data RAM is made accurate and efficient, and the transmission-throughput in case of DMA transmission is improved.

4. 发明专利

JPS61248143A LSI SYSTEM CONNECTING REGISTER IN PARALLEL AND HIERARCHICALLY 失效
公开(公告)号：JPS61248143A
公开(公告)日：1986-11-05
申请号：JP8853585
申请日：1985-04-26
申请人： HITACHI LTD
发明人： SATOU TOMORU , KANEKO KENJI , UEDA HIROTADA , HAGIWARA YOSHIMUNE , MATSUSHIMA HITOSHI , NAKAGAWA TETSUYA , KIUCHI ATSUSHI
IPC分类号： G06F11/00 , G06F11/07 , G06F11/30 , G06F11/36
摘要： PURPOSE:To make it possible to monitor the internal state of an LSI system without increasing the number of address signals and the number of pins by connecting status registers in parallel and hierarchically and enabling to transfer the content of each register to an output register through a bus. CONSTITUTION:Among various information indicating internal stage, information that needs the stopping of the system according to error state, and error information necessary for program debugging and a system debugging are stored in an ERR 32. The informations are classified and decoded by a decoder 37 and reflected to an STR 31 together with other information, and the outlines of the state of operation and error can be known by monitoring the STR 31. Detailed error information is stored in the ERR 32, and the ERR 32 is connected with an OR 30 through a bus. On receiving command from a CPU, the ERR 32 transfers the information to the OR 30 once and then reads out. New address signal by the increase of ERR 32 is not necessary and accordingly, it is not necessary to increase the number of pins.

5. 发明专利

JPS6352256A CONTROL SYSTEM FOR DATA TRANSFER 失效
公开(公告)号：JPS6352256A
公开(公告)日：1988-03-05
申请号：JP19530486
申请日：1986-08-22
申请人： HITACHI LTD
发明人： SATOU TOMORU
IPC分类号： G06F15/16 , G06F13/28 , G06F15/177
摘要： PURPOSE:To perform the sequential transfer of data with no intervention of interruption processing by carrying out the internal transfer of data according to the change of the set control data when an action is indicated based on a fact that an instruction exclusive for data transfer is set. CONSTITUTION:When an action based on a fact that an instruction exclusive for data transfer is indicated under the control of a direct memory access controller DMAC, the internal transfer of data is carried out according to the output of the data to be transferred to the outside or the change of the data to be received from the outside. Thus the internal transfer of data is carried out sequentially with no intervention of interruption processing by setting the change of the control data under a queuing state. In such a way, the data transfer to the outside is secured with high efficiency and with no increase of hardware.

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