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1. 发明专利

JP2013119458A Elevator equipment 审中-公开
标题翻译：电梯设备
公开(公告)号：JP2013119458A
公开(公告)日：2013-06-17
申请号：JP2011267773
申请日：2011-12-07
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SAKAI YUJI , ZAMA HIDETAKA , SAKAI MITSURU
IPC分类号： B66B1/42 , B66B1/44 , B66B7/08
摘要： PROBLEM TO BE SOLVED: To provide elevator equipment capable of obtaining an elevator car position adjusting means with a short adjustment stroke.SOLUTION: The elevator equipment includes a sliding body position detector 11 which detects a position at which a sliding body 7a is located, the position of an adjustment stroke possessed by an elevator car position adjusting means 7, a load measurement means 12 for measuring a movable load of an elevator car 2, and a control means for adjusting in advance a position of the sliding body by determining a range of an increase/decrease in a movable load on a next target floor on the basis of the movable load on a landing floor 6. Before an elevator car moves to the next target floor after correcting a level displacement, the movable load of the elevator car is measured, an increase/decrease range in the movable load, for example, by the load/unload of a passenger on the next target floor is determined, and a level displacement amount due to an increase/decrease in the movable load is calculated. On the basis of the result of this calculation, before the elevator car reaches the target floor, a sliding body is moved in advance to a position where a predicted level displacement can be corrected.
摘要翻译：要解决的问题：提供能够获得具有短调节行程的电梯轿厢位置调节装置的电梯设备。解决方案：电梯设备包括滑动体位置检测器11，其检测滑动体7a所在的位置，电梯轿厢位置调节装置7所具有的调节冲程的位置，负载测量装置12，用于测量电梯轿厢2的可移动负载;以及控制装置，用于通过基于可移动负载确定下一个目标楼层上的可移动负载的增加/减少的范围来预先调整滑动体的位置着陆层6.在校正水平位移之前电梯轿厢移动到下一个目标楼层之前，测量电梯轿厢的可移动负载，例如可移动负载的增减范围，例如通过装载/卸载确定下一个目标楼层的乘客，并且计算由于可移动负载的增加/减少引起的水平位移量。基于该计算结果，在电梯轿厢到达目标楼层之前，将滑动体预先移动到可以校正预测水平位移的位置。版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2012066907A Braking device for elevator, and elevator device using the same 有权
标题翻译：用于电梯的制动装置和使用它的电梯装置
公开(公告)号：JP2012066907A
公开(公告)日：2012-04-05
申请号：JP2010213008
申请日：2010-09-24
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SAKAI YUJI , ZAMA HIDETAKA , HIRANO KAORU , HANEDA MASAHIDE
IPC分类号： B66B5/18 , B66B11/08
摘要： PROBLEM TO BE SOLVED: To provide a braking device for an elevator, which can move an elevating body when a power supply for energizing an actuator of the braking device cannot be secured, and to provide an elevator device using the braking device.SOLUTION: The braking device 10 of the elevator and the braking device 10 equipped with the elevator device are arranged in a pair facing each other and includes: operating arms 14 provided rotatably around a shaft 11 serving as a fulcrum; an operating braking part 17; a spring 15; an actuator 16; and a braking member for braking the elevating body in association with the contact of the operating braking part 17 with a pressed member 7. The braking device for the elevator is provided at the elevating body, and an invalidating stopper 22 preventing the contact of the operating braking part 17 with the pressed member 7 against the spring force of the spring 15 of the operating arms 14 can be mounted in the intercepted state of energization to the actuator 16.
摘要翻译：要解决的问题：提供一种用于电梯的制动装置，当不能确保用于激励制动装置的致动器的电源时，能够使升降体移动，并且提供使用该制动装置的电梯装置。解决方案：电梯的制动装置10和装备有电梯装置的制动装置10彼此面对地布置，并且包括：可旋转地围绕作为支点的轴11设置的操作臂14; 操作制动部17; 春天15 致动器16; 以及用于与操作制动部件17与被按压部件7的接触相关联地制动升降体的制动部件。电梯的制动装置设置在升降体上，防止止动件22阻止操作的接触制动部分17克服了操作臂14的弹簧15的弹簧力，被按压的构件7可以被安装在致动器16的通电状态中。（C）2012年，JPO和INPIT

3. 发明专利

JPH08287675A STORAGE 失效
公开(公告)号：JPH08287675A
公开(公告)日：1996-11-01
申请号：JP11532995
申请日：1995-04-18
申请人： HITACHI LTD
发明人： HASEGAWA MASATOSHI , KAJITANI KAZUHIKO , OOISHI TSURATOKI , SAKAI YUJI
IPC分类号： G11C11/401
摘要： PURPOSE: To speed up the machine cycle such as a computer, etc., by speeding up mean access time of a main storage MM consisting of a dynamic RAM, etc. CONSTITUTION: The dynamic RAM constituting the main storage MM of a computer is divided into e.g. 64 pieces of banks BANKO-BANK63, and these storage areas are dispersedly allocated to respective jobs, and e.g. 16 pieces of banks are combined according to access frequencies of respective jobs, and then, the addresses with the high probability accessed from a system side are made simultaneously to be in a previously selected state. Thus, an incorporated central processing unit MCPU of a stored program system for controlling access conditions of respective jobs and simultaneously deciding the combination of the banks to be made to be in a previously selected state and its row address is provided in the main storage. Thus, when the bank to be made to be in the previously selected state is hit on the bank accessed really, the access time of the main storage MM is shortened to only the time required for the column selection of the dynamic RAM.

4. 发明专利

JPH0785697A TEST METHOD FOR SEMICONDUCTOR MEMORY AND ITS TEST SYSTEM 失效
公开(公告)号：JPH0785697A
公开(公告)日：1995-03-31
申请号：JP23181993
申请日：1993-09-17
申请人： HITACHI LTD
发明人： SAKAI YUJI , OSHIMA KAZUYOSHI , SAWADA JIRO
IPC分类号： G01R31/26 , G01R31/28 , G11C29/00 , G11C29/56
摘要： PURPOSE:To easily recognize a defect occurring condition and to shorten a time for analyzing a defect by sampling a defective bit relating to a specific defective mode. CONSTITUTION:Only a defective bit relating to a specific defective mode specified by a defect setting means 4 is sampled out of defective bits of a LS11 detected by a tester 10 with a measuring condition set by a condition setting means 2 in a defective address analyzing means 3, sent to a display means 5 and a distribution condition of defective bits is displayed, and the occurring condition of a defective mode is recognized. And when the specific defective mode is discriminated and measuring range and measuring condition required for analyzing is informed to the condition setting means 2, a controller 11 sends a signal required for a test from a power supply section 17 and a pattern generator 12 to the LS 11, read-out data is compared with write-in data in a comparator means 14, and normal/defective condition is discriminated. Thus, analyzing a cause of it occurrence of a defect can be performed quickly and easily by sampling a specific defective mode out of mixed defective modes and clarifying a defective object to be analyzed.

5. 发明专利

JPH03214669A SEMICONDUCTOR STORAGE DEVICE AND REDUNDANT MEMORY REPAIR METHOD 失效
公开(公告)号：JPH03214669A
公开(公告)日：1991-09-19
申请号：JP6584089
申请日：1989-03-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAJITANI KAZUHIKO , YAMAGUCHI YASUNORI , OSHIMA KAZUYOSHI , YAMAZAKI TAKASHI , MIYAMOTO EIJI , SAKAI YUJI , SAWADA JIRO , ETO JUN , HORIGUCHI SHINJI , IKENAGA SHINICHI , KUMADA ATSUSHI , TSUNOSAKI MANABU , KASAMA YASUHIRO , UDO SHINJI , YOSHIOKA HIROSHI , SAITO HIROMI , TAKANO MITSUHIRO , MORINO MAKOTO , MIYATAKE SHINICHI , MATSUMOTO TETSUO
IPC分类号： G11C11/41 , G11C11/401 , G11C11/407 , G11C11/409 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PURPOSE:To attain a high speed and also a large storage capacity by disposing peripheral circuits in cross areas formed of a longitudinal central part and a lateral central part and by disposing memory arrays in four regions divided by the cross areas. CONSTITUTION:In a semiconductor chip or in each of areas divided by the longitudinal center line thereof, peripheral circuits are disposed in cross areas A to E formed of the longitudinal central part and the lateral central part thereof, while memory arrays M are disposed in four regions divided by the cross areas A to E. As the peripheral circuits are disposed in the central parts of the chip or in each of the areas according to this constitution, the maximum transmission path of signals can be shortened to the half of a chip size substantially, and therefore DRAM designed to have a large storage capacity can be made to operate at a high speed.

6. 发明专利

JPH09106669A SYNCHRONOUS DRAM AND SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH09106669A
公开(公告)日：1997-04-22
申请号：JP22181896
申请日：1996-08-05
申请人： HITACHI LTD
发明人： SAKAI YUJI , OOISHI TSURATOKI
IPC分类号： G11C11/407 , G11C11/401
摘要： PROBLEM TO BE SOLVED: To perform the data input and output in image processing at a high speed simply by automatically generating commands and address signals to the other memory bank inside following the access to one memory bank, and performing accessing. SOLUTION: When a memory cell corresponding to a burst length is accessed in the synchronous DRAMs of memory array banks 200A and 200B, whether a plurality of memory cells are arranged striding over one memory bank and the other memory bank or not, is detected. When the striding arrangement is detected, commands and address signals required for the memory cells of the other memory bank are automatically generated inside following the access to the memory cells of one memory bank, and the accessing is performed. Thus, a high-speed access in a burst mode can be performed at the arbitrary display area on the screen.

7. 发明专利

JPH09102592A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH09102592A
公开(公告)日：1997-04-15
申请号：JP8991196
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAJITANI KAZUHIKO , YAMAGUCHI YASUNORI , OSHIMA KAZUYOSHI , YAMAZAKI TAKASHI , MIYAMOTO EIJI , SAKAI YUJI , SAWADA JIRO , ETO JUN , HORIGUCHI SHINJI , IKENAGA SHINICHI , KUMADA ATSUSHI , TSUNOSAKI MANABU , KASAMA YASUHIRO , UDO SHINJI , YOSHIOKA HIROSHI , SAITO HIROMI , TAKANO MITSUHIRO , MORINO MAKOTO , MIYATAKE SHINICHI , MATSUMOTO TETSUO
IPC分类号： G11C11/401 , H01L21/82 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To increase the memory capacity or large scale integration by providing a step buffer area made of a dummy conductor layer between a memory array and a peripheral circuit by sing a plurality of dynamic memory cells having a laminated capacitor as a memory cell formed in the memory array. SOLUTION: A memory chip has memory arrays M divided into four by cross areas made of areas A to E. The arrays M divided into the four are disposed by extending a word line in the lateral direction, and disposed by extending a data line (bit line or digit line) in a vertical direction. A step buffer area made of a dummy wiring layer is provided between the arrays M and the peripheral circuit. A guard ring is disposed under the step buffer area to stabilize the characteristics.

8. 发明专利

JPS6173375A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS6173375A
公开(公告)日：1986-04-15
申请号：JP19466884
申请日：1984-09-19
申请人： Hitachi Ltd
发明人： SAKAI YUJI , SATO KATSUYUKI
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/78 , H02H7/20 , H03K19/003
CPC分类号： H02H7/20 , H03K19/00315
摘要： PURPOSE:To improve the electrical reliability of a semiconductor integrated circuit device by forming semiconductor elements having different electrostatic breakdown strength, arranging these semiconductor elements in order of higher electrostatic breakdown strength and constituting an electrostatic breakdown preventive circuit. CONSTITUTION:An electrostatic breakdown preventive circuit II is interposed between an external input terminal BP and an input step circuit I. The circuit II is constituted by a MISFET Q1 having a high threshold and high electrostatic breakdown strength and a MISFET Q2 having threshold voltage lower than the MISFET Q1 and electrostatic breakdown strength lower than the MISFET Q1. The circuit II is also constituted by a resistor R1 constituted by a semiconductor region having high electrostatic breakdown strength and a resistor element R2 constituted by a semiconductor region having low electrostatic breakdown strength. Consequently, excess voltage generating electrostatic breakdown can be lowered to a predetermined voltage level by stages. Accordingly, the concentration of excess currents to one semiconductor element in semiconductor elements constituting the circuit II can be prevent, thus obviating the breakdown of the circuit II.
摘要翻译：目的：为了通过形成具有不同静电击穿强度的半导体元件来提高半导体集成电路器件的电可靠性，按照更高的静电击穿强度的顺序布置这些半导体元件并构成静电击穿防止电路。构成：静电击穿防止电路II插入在外部输入端子BP和输入步进电路I之间。电路II由具有高阈值和高静电击穿强度的MISFET Q1和阈值电压低于的MISFET Q2构成 MISFET Q1和静电击穿强度低于MISFET Q1。电路II还由具有高静电击穿强度的半导体区域构成的电阻器R1和由具有低静电击穿强度的半导体区域构成的电阻元件R2构成。因此，产生过电压的静电击穿可以逐级降低到预定的电压水平。因此，可以防止构成电路II的半导体元件中的一个半导体元件的过剩电流的集中，从而避免电路II的击穿。

9. 发明专利

JP2015003799A エレベーターのテールコードの制振装置审中-公开
标题翻译：电梯尾绳的振动控制装置
公开(公告)号：JP2015003799A
公开(公告)日：2015-01-08
申请号：JP2013130134
申请日：2013-06-21
申请人：株式会社日立製作所 , Hitachi Ltd
发明人： SAKAI YUJI , SAKAI MITSURU , HIRANO KAORU , SEKIYA YUJI
IPC分类号： B66B7/06
摘要：【課題】乗りかごが最下階に位置している場合でも、テールコードの揺れを簡易な構造で抑制できるエレベーターのテールコードの制振装置を提供する。【解決手段】乗りかご1が昇降する昇降路20の壁面と乗りかご1との間に架け渡され乗りかご1の昇降により変位するテールコード2の揺れを抑制するエレベーターのテールコードの制振装置において、一端側は、乗りかご1の下部に接続され、他端側は、テールコード2に当接する。他端側とテールコード2とが当接する位置は、テールコード2の変位により変位可能である。他端側は、乗りかご1が最下階に位置しているときに、テールコード2の鉛直方向最下部に形成された屈曲部2Rに当接してテールコード2に張力を与える。【選択図】図1
摘要翻译：要解决的问题：提供一种用于电梯尾绳的振动控制装置，其能够通过简单的结构抑制尾绳的摆动，即使当汽车位于最低楼层时。解决方案：在用于电梯的振动控制装置轿厢1向上下移动的升降道20的壁面之间的尾巴和能够抑制轿厢1上下移动时的尾绳2的摆动的轿厢1，一端侧与轿厢1的下部，而另一端侧与尾绳2接触。另一端侧接触尾绳2的位置可以通过尾绳2的位移而移位。当轿厢1为位于最低层，另一端接触形成在尾绳2的垂直方向上的最下部的弯曲部分2R，并向尾绳2施加张力。

10. 发明专利

JP2014125305A Tail cord active vibration controller for elevator 审中-公开
标题翻译：拖拉机主动振动控制器
公开(公告)号：JP2014125305A
公开(公告)日：2014-07-07
申请号：JP2012282731
申请日：2012-12-26
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： USHIMURA MASATO , SAKAI MITSURU , SAKAI YUJI
IPC分类号： B66B7/06
摘要： PROBLEM TO BE SOLVED: To provide a tail cord active vibration controller for an elevator capable of controlling active vibration caused by resonance of a tail cord caused by building vibration with a simple structure.SOLUTION: The tail cord active vibration controller for an elevator which is hung between a car 2 and a hoistway wall 1a in a hoistway 1 in which the car 2 is lifted up and down and suppresses vibration of plural tail cords 3 which displace in a vertical direction of the hoistway 1 according to lifting up and down of the car 2 is provided. Face fasteners 5 are attached to the respective tail cords 3 with a predetermined interval and the face fasteners 5 of adjacent tail cords 3 are disposed so as to face each other.
摘要翻译：要解决的问题：提供一种用于电梯的尾绳主动振动控制器，其能够以简单的结构控制由建筑物振动引起的尾绳共振引起的主动振动。解决方案：用于电梯的尾绳主动振动控制器悬挂在轿厢2和升降道1中的井道壁1a之间，其中轿厢2被上下升起，并且抑制沿着井道1的垂直方向位移的多个尾绳3的振动，提供车2。面紧固件5以预定间隔附接到相应的尾绳3，并且相邻尾线3的面紧固件5被布置成彼此面对。

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