专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08589775B2 Error tolerant flip-flops 有权
标题翻译：容错触发器
公开(公告)号：US08589775B2
公开(公告)日：2013-11-19
申请号：US13047090
申请日：2011-03-14
申请人： Georg Georgakos , Michael Goessel , Anton Huber
发明人： Georg Georgakos , Michael Goessel , Anton Huber
IPC分类号： G06F11/00
CPC分类号： G11C11/419 , G06F11/1032 , G11C2029/0411
摘要： One embodiment of the present invention relates to an error tolerant memory circuit having a low hardware overhead that can tolerate both single volatile soft errors and permanent errors. In one embodiment, the method and apparatus comprise a memory circuit having a plurality of memory element pairs, respectively having two memory storage elements configured to store a data unit. One or more parity generation circuits are configured to calculate a first parity bit from data written to the plurality of memory element pairs (e.g., the two memory storage elements) and a second parity bit from data read from one of the two memory storage elements in the plurality of memory element pairs. Based upon the calculated first and second parity bits, the memory circuit chooses to selectively output data from memory storage elements not known to contain an error.
摘要翻译：本发明的一个实施例涉及具有低硬件开销的容错存储器电路，其可容忍单个易失性软错误和永久错误。在一个实施例中，该方法和装置包括具有多个存储元件对的存储器电路，其分别具有被配置为存储数据单元的两个存储器存储元件。一个或多个奇偶校验生成电路被配置为从从两个存储器元件对（例如，两个存储器元件）中写入的数据中计算第一奇偶校验位，并且从位于多个存储元件对。基于计算的第一和第二奇偶校验位，存储器电路选择选择性地从不知道包含错误的存储器存储元件输出数据。

2. 发明授权

US08539321B2 Apparatus and method for correcting at least one bit error within a coded bit sequence 有权
标题翻译：用于校正编码比特序列内的至少一个比特差错的装置和方法
公开(公告)号：US08539321B2
公开(公告)日：2013-09-17
申请号：US12943520
申请日：2010-11-10
申请人： Thomas Kern , Ulrich Backhausen , Michael Goessel , Thomas Rabenalt , Stéphane Lacouture
发明人： Thomas Kern , Ulrich Backhausen , Michael Goessel , Thomas Rabenalt , Stéphane Lacouture
IPC分类号： H04M13/00
CPC分类号： H03M13/151 , H03M13/152 , H03M13/155 , H03M13/1575 , H03M13/159 , H03M13/616 , H03M13/6575
摘要： An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence.
摘要翻译：用于校正编码比特序列中的至少一个比特误差的装置包括误差校正子发生器和比特误差校正器。错误校正子发生器确定通过校验矩阵与编码比特序列的乘法导出的编码比特序列的错误校正。

3. 发明申请

US20130173979A1 HIGH PERFORMANCE COMPACTION FOR TEST RESPONSES WITH MANY UNKNOWNS 有权
标题翻译：高性能压力测试响应与多个知识
公开(公告)号：US20130173979A1
公开(公告)日：2013-07-04
申请号：US13643107
申请日：2011-05-18
申请人： Michael Goessel , Michael Richter , Thomas Rabenalt
发明人： Michael Goessel , Michael Richter , Thomas Rabenalt
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/318547 , G01R31/318563 , G01R31/318583
摘要： A circuit arrangement for controlling the masking of test and diagnosis data with X values of an electronic circuit with N scan paths, wherein the test data are provided on insertion into the N scan paths by a decompressor with m inputs and N outputs (m
摘要翻译：一种电路装置，用于利用具有N个扫描路径的电子电路的X值来控制对测试和诊断数据的掩蔽，其中测试数据在由具有m个输入和N个输出的解压缩器插入到N个扫描路径中时提供（m

4. 发明申请

US20120144260A1 Apparatus and Method for Detecting an Error Within a Coded Binary Word 有权
标题翻译：用于检测编码二进制字中的错误的装置和方法
公开(公告)号：US20120144260A1
公开(公告)日：2012-06-07
申请号：US12959838
申请日：2010-12-03
申请人： Thomas Kern , Ulrich Backhausen , Michael Goessel , Thomas Rabenalt
发明人： Thomas Kern , Ulrich Backhausen , Michael Goessel , Thomas Rabenalt
IPC分类号： G06F11/10
CPC分类号： H03M13/3776 , H03M13/13 , H03M13/19 , H03M13/3738
摘要： An apparatus for detecting an error within a coded binary word includes an error corrector and an error detector. The error corrector corrects a correctable bit error within a faulty subset of bits of a faulty coded binary word coded by an error correction code, so that the corrected subset of bits is equal to a corresponding subset of bits of a code word of the error correction code, if the error corrector works faultlessly. Further, the error detector determines an error detection bit sequence indicating whether or not an error detector input binary word is a code word of the error correction code. The error detector input binary word is based on a corrected coded binary word containing the corrected subset of bits and maximally a proper subset of bits of the faulty coded binary word.
摘要翻译：用于检测编码二进制字中的误差的装置包括误差校正器和误差检测器。误差校正器校正由错误校正码编码的故障编码二进制字的位的有故障子集内的可校正位错误，使得校正的位子集等于纠错码字的相应子集代码，如果错误校正器工作无效。此外，误差检测器确定指示误差检测器输入二进制字是否是纠错码的码字的错误检测比特序列。误差检测器输入二进制字基于包含校正的比特子集的校正的编码二进制字，并且最大限度地存在故障编码的二进制字的位的适当子集。

5. 发明授权

US07870473B2 Error detection device for an address decoder, and device for error detection for an address decoder 有权
标题翻译：用于地址解码器的错误检测装置，以及用于地址解码器的错误检测装置
公开(公告)号：US07870473B2
公开(公告)日：2011-01-11
申请号：US11672638
申请日：2007-02-08
申请人： Michael Goessel , Franz Klug , Jorge Guajardo Merchan , Steffen Marc Sonnekalb
发明人： Michael Goessel , Franz Klug , Jorge Guajardo Merchan , Steffen Marc Sonnekalb
IPC分类号： G06F7/02 , H03M13/00
CPC分类号： G06F11/1016
摘要： An error detection device for an address decoder converting an input address to an associated output address out of a plurality of valid output addresses using a 1-out-of-n decoder, the error detection device including a regenerator for generating a regenerated address on the basis of the output address from the 1-out-of-n decoder, and a comparer for receiving the input address and the regenerated address and to output a signal, on the basis of a comparison of the input address and the regenerated address, which indicates an error in the conversion of the input address to the output address if the input address and the regenerated address do not match, and which indicates an error-free conversion of the input address to the output address if the input address equals the regenerated address.
摘要翻译：一种用于地址解码器的错误检测装置，其使用1-out-n解码器将多个有效输出地址中的输入地址转换为相关联的输出地址，所述错误检测装置包括：再生器，用于在基于1输出解码器的输出地址的基础，以及用于接收输入地址和再生地址并根据输入地址和再生地址的比较输出信号的比较器，其中如果输入地址和再生地址不匹配，则表示输入地址转换为输出地址的错误，如果输入地址等于重新生成的地址，则表示输入地址无误转换为输出地址。

6. 发明申请

US20080244346A1 Circuit for Compression and Storage of Circuit Diagnosis Data 有权
标题翻译：电路诊断数据的压缩和存储电路
公开(公告)号：US20080244346A1
公开(公告)日：2008-10-02
申请号：US12124196
申请日：2008-05-21
申请人： Frank Poehl , Jan Rzeha , Matthias Beck , Michael Goessel , Peter Muhmenthaler
发明人： Frank Poehl , Jan Rzeha , Matthias Beck , Michael Goessel , Peter Muhmenthaler
IPC分类号： G01R31/28
CPC分类号： G01R31/318335 , G01R31/31813
摘要： A compactor includes test data inputs that are connectable to circuit outputs of an electrical circuit, test comparison inputs, and test data outputs. The compactor further includes a number of H matrix XOR gates arranged as a switching mechanism between the test data inputs and the test data outputs such that data applied to the test data inputs is produced at the test data outputs compressed in accordance with coefficients of an H matrix of an error-correcting code, and compensation XOR gates arranged between the test data inputs and the test data outputs, each compensation XOR gate including an input for receiving a compensation value.
摘要翻译：压实机包括可连接到电路的电路输出，测试比较输入和测试数据输出的测试数据输入。压实机还包括多个H矩阵XOR门，其被布置为在测试数据输入和测试数据输出之间的切换机构，使得施加到测试数据输入的数据在根据H的系数压缩的测试数据输出处产生纠错码的矩阵，以及布置在测试数据输入和测试数据输出之间的补偿XOR门，每个补偿XOR门包括用于接收补偿值的输入。

7. 发明授权

US08966355B2 Apparatus and method for comparing pairs of binary words 有权
标题翻译：用于比较双字对的装置和方法
公开(公告)号：US08966355B2
公开(公告)日：2015-02-24
申请号：US13430147
申请日：2012-03-26
申请人： Thomas Kern , Ulrich Backhausen , Michael Goessel , Thomas Rabenalt
发明人： Thomas Kern , Ulrich Backhausen , Michael Goessel , Thomas Rabenalt
IPC分类号： H03M13/00 , G06F11/00 , H03M13/37 , H03M13/15 , H03M13/03 , H03M13/19 , H03M13/29 , H03M13/25 , G06F11/10 , G06F11/14
CPC分类号： H03M13/3746 , G05B9/03 , G05B19/0428 , G06F11/00 , G06F11/1048 , G06F11/1479 , G06F11/1641 , H03M13/033 , H03M13/155 , H03M13/19 , H03M13/258 , H03M13/2948 , H03M13/2957 , H03M13/2966 , H03M13/299 , H03M13/37 , H03M13/3738 , H03M13/3784 , H03M13/6575
摘要： An apparatus for comparing pairs of binary words includes an intermediate value determiner and an error detector. The intermediate value determiner determines an intermediate binary word so that the intermediate binary word is equal to a reference binary word for a first pair of equal or inverted binary words, so that the intermediate binary word is equal to the inverted reference binary word for a second pair of equal or inverted binary words and so that the intermediate binary word is unequal to the reference binary word and the inverted reference binary word for a pair of unequal and uninverted binary words, if the intermediate value determiner works faultlessly. Further, the error detector provides an error signal based on the intermediate binary word so that the error signal indicates whether or not the binary words of a pair of binary words are equal or inverted.
摘要翻译：用于比较二进制字对的装置包括中间值确定器和误差检测器。中间值确定器确定中间二进制字，使得中间二进制字等于第一对相等或反转二进制字的参考二进制字，使得中间二进制字等于第二对的反转参考二进制字如果中间值确定器无故障地工作，则使中间二进制字不对等于参考二进制字和反向参考二进制字，用于一对不等的和未反相的二进制字。此外，误差检测器基于中间二进制字提供误差信号，使得误差信号指示一对二进制字的二进制字是否相等或反转。

8. 发明授权

US08631308B2 Apparatus and method for determination of a position of a 1 bit error in a coded bit sequence, apparatus and method for correction of a 1-bit error in a coded bit sequence and decoder and method for decoding an incorrect, coded bit sequence 有权
标题翻译：用于确定编码比特序列中的1比特错误的位置的装置和方法，用于校正编码比特序列和解码器中的1比特错误的装置和方法以及用于对不正确的编码比特序列进行解码的方法
公开(公告)号：US08631308B2
公开(公告)日：2014-01-14
申请号：US13248502
申请日：2011-09-29
申请人： Michael Goessel , Michael Richter
发明人： Michael Goessel , Michael Richter
IPC分类号： H03M13/00
CPC分类号： H03M13/2906 , H03M13/19 , H03M13/21 , H03M13/6502 , H03M13/6575
摘要： An apparatus for determination of a position of a 1-bit error includes an error position determiner of the inner code, an error syndrome determiner of the outer code, a derivative determiner and an overall error position determiner. The error position determiner of the inner code determines at least one possible error position of a bit error in the coded bit sequence on the basis of the inner code. The error syndrome determiner of the outer code determines a value of a non-linear syndrome bit of the outer code on the basis of a non-linear function of bits in the coded bit sequence. Furthermore, the derivative determiner determines a value of a derivative bit for at least one determined, possible error position of the bit error on the basis of derivation of the non-linear function based on the bit at the determined, possible error position in the coded bit sequence.
摘要翻译：用于确定1位错误位置的装置包括内码的错误位置确定器，外码的误差校正器确定器，导数确定器和总错误位置确定器。内部代码的错误位置确定器基于内部代码确定编码比特序列中的位错误的至少一个可能的错误位置。外码的误差校正器确定器基于编码比特序列中的比特的非线性函数来确定外码的非线性校正子比特的值。此外，导数确定器基于基于所确定的编码的可能错误位置中的位的非线性函数的导出，确定位误差的至少一个确定的可能错误位置的微分位的值。位序列。

9. 发明申请

US20130212441A1 System and Method for Signature-Based Redundancy Comparison 有权
标题翻译：基于签名的冗余比较系统与方法
公开(公告)号：US20130212441A1
公开(公告)日：2013-08-15
申请号：US13430126
申请日：2012-03-26
申请人： Antonio Vilela , Rainer Faller , Michael Goessel , Simon Brewerton , Glenn Ashley Farrall , Neil Stuart Hastie , Boyko Traykov , David Addison , Klaus Oberlaender , Thomas Rabenalt
发明人： Antonio Vilela , Rainer Faller , Michael Goessel , Simon Brewerton , Glenn Ashley Farrall , Neil Stuart Hastie , Boyko Traykov , David Addison , Klaus Oberlaender , Thomas Rabenalt
IPC分类号： G06F11/07
CPC分类号： H03M13/3746 , G05B9/03 , G05B19/0428 , G06F11/00 , G06F11/1048 , G06F11/1479 , G06F11/1641 , H03M13/033 , H03M13/155 , H03M13/19 , H03M13/258 , H03M13/2948 , H03M13/2957 , H03M13/2966 , H03M13/299 , H03M13/37 , H03M13/3738 , H03M13/3784 , H03M13/6575
摘要： A system and method for signature-based redundancy comparison provides for receiving, by a master part, an input signal and generating, by the master part, a binary output signal, generating a delayed input signal based on the input signal, generating a first output signature based on the binary output signal, and generating a delayed first output signature based on the first output signature. The system and method further comprise generating a delayed binary output signal based on the delayed input signal, generating, by a checker part, a delayed second output signature based on the delayed binary output signal, comparing the delayed first output signature with the delayed second output signature, and generating an error signal, where the state of the error signal is based upon the comparison.
摘要翻译：一种用于基于签名的冗余比较的系统和方法，用于由主机部分接收输入信号，并由主机部分产生二进制输出信号，基于输入信号产生延迟的输入信号，产生第一输出基于所述二进制输出信号的签名，以及基于所述第一输出签名生成延迟的第一输出签名。该系统和方法还包括基于延迟的输入信号产生延迟的二进制输出信号，由检验器部分基于延迟的二进制输出信号产生延迟的第二输出签名，将延迟的第一输出签名与延迟的第二输出进行比较签名并产生误差信号，其中误差信号的状态基于比较。

10. 发明授权

US08060800B2 Evaluation circuit and method for detecting and/or locating faulty data words in a data stream Tn 有权
标题翻译：用于检测和/或定位数据流Tn中的故障数据字的评估电路和方法
公开(公告)号：US08060800B2
公开(公告)日：2011-11-15
申请号：US10577288
申请日：2004-10-22
申请人： Michael Goessel , Andreas Leininger , Heinz Mattes , Sebastian Sattler
发明人： Michael Goessel , Andreas Leininger , Heinz Mattes , Sebastian Sattler
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31932 , G01R31/31703
摘要： An evaluation circuit and method for detecting faulty data words in a data stream is disclosed. In one embodiment the evaluation circuit according to the invention includes a first linear automaton circuit and also a second linear automaton circuit connected in parallel, each having a set of states z, which have a common input line for receiving a data stream Tn. The first linear automaton circuit and the second linear automaton circuit are designed such that a first signature and a second signature, respectively, can be calculated. Situated downstream of the two linear automaton circuits are respectively a first logic combination gate and a second logic combination gate, which compare the signature respectively calculated by the linear automaton circuit with a predeterminable good signature and output a comparison value.
摘要翻译：公开了一种用于检测数据流中的错误数据字的评估电路和方法。在一个实施例中，根据本发明的评估电路包括并联连接的第一线性自动机电路和第二线性自动机电路，每个具有一组状态z，其具有用于接收数据流Tn的公共输入线。第一线性自动机电路和第二线性自动机电路被设计成可以分别计算第一签名和第二签名。位于两个线性自动机电路的下游分别是第一逻辑组合门和第二逻辑组合门，其将由线性自动机电路分别计算的签名与可预定的良好签名进行比较并输出比较值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式