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1. 发明授权

US3874937A Method for manufacturing metal oxide semiconductor integrated circuit of reduced size 失效
标题翻译：制造减少金属氧化物半导体集成电路的方法
公开(公告)号：US3874937A
公开(公告)日：1975-04-01
申请号：US41144473
申请日：1973-10-31
申请人： GEN INSTRUMENT CORP
发明人： HUBER ROBERT J , SMITH KENT F
IPC分类号： H01L21/00 , H01L21/265 , H01L29/00 , H01L29/76 , H01L7/54
CPC分类号： H01L29/00 , H01L21/00 , H01L21/265 , H01L29/76
摘要： A metal oxide semiconductor integrated circuit of reduced size and a method for manufacturing same wherein the size reduction results from the elimination of the usual dimensional tolerances on the width of the gate electrode of the transistors therein. Misalignment of the gate electrode along the width of the underlying thin insulating layer of the channel region, which normally causes degraded performance, is compensated for by implanting ions of the same conductivity determining type as the original substrate in the channel region beneath the areas of the thin insulating layer exposed by the misalignment. No additional masking operation is necessary. The implanted ions prevent the formation of an uncontrollable conducting path between the source and drain regions normally caused by this misalignment, thus eliminating the necessity for the use of an oversized gate electrode to insure that exposed areas of the thin insulating layer are not present. The use of smaller gate electrodes substantially reduces the size of the transistors and therefore the entire circuit.

2. 发明授权

US3870901A Method and apparatus for maintaining the charge on a storage node of a mos circuit 失效
标题翻译：用于维护MOS电路存储节点上的电荷的方法和装置
公开(公告)号：US3870901A
公开(公告)日：1975-03-11
申请号：US42342273
申请日：1973-12-10
申请人： GEN INSTRUMENT CORP
发明人： SMITH KENT F , HUBER ROBERT J
IPC分类号： G11C11/402 , G11C11/406 , G11C11/412 , G11C11/417 , H01L21/822 , H01L27/04 , H03K3/356 , H03K17/00 , H03K17/24 , H03K3/286 , G11C11/38 , H03K3/33
CPC分类号： G11C11/417 , G11C11/4023 , G11C11/406 , G11C11/412 , H03K3/356 , H03K3/356052 , H03K3/356104 , H03K17/24 , H03K2217/0036
摘要： Method and apparatus for maintaining the charge on a storage node of a MOS circuit of the type having a depletion mode transistor as a load resistor situated between a voltage source and a storage node. The voltage level of the storage node determines the output of the circuit. The storage node is charged to a first voltage level upon the receipt of a given data input to the circuit. The substrate of the circuit is reversed biased to a level sufficient to render the depletion mode transistor nonconducting. This will isolate the storage node and isolation will continue for a time selected to maintain a residual charge of a given magnitude on the storage node if the node was originally charged. The substrate bias is removed to permit the depletion mode transistor to again become conductive. If the residual charge was present on the storage node, the node is permitted to recharge thus returning the node to the first voltage level and re-establishing the output of the circuit. In this way power consumption is minimized while the state of the circuit is maintained.
摘要翻译：用于将具有耗尽型晶体管的MOS电路的存储节点上的电荷维持为位于电压源和存储节点之间的负载电阻器的方法和装置。存储节点的电压电平决定电路的输出。在接收到输入到电路的给定数据时，存储节点被充电到第一电压电平。电路的衬底被反向偏置到足以使耗尽型晶体管不导通的电平。这将隔离存储节点，并且如果节点最初被充电，则隔离将在所选择的时间内持续一段时间以保持存储节点上的给定幅度的剩余电荷。去除衬底偏置以使耗尽型晶体管再次变成导电。如果存储节点上存在剩余电荷，则允许节点进行充电，从而将节点返回到第一电压电平并重新建立电路的输出。以这种方式，电力消耗被最小化，同时维持电路的状态。

3. 发明授权

US3922704A Metal oxide semiconductor integrated circuit of reduced size and a method for manufacturing same 失效
标题翻译：尺寸减小的金属氧化物半导体集成电路及其制造方法
公开(公告)号：US3922704A
公开(公告)日：1975-11-25
申请号：US52028474
申请日：1974-11-04
申请人： GEN INSTRUMENT CORP
发明人： HUBER ROBERT J , SMITH KENT F
IPC分类号： H01L21/00 , H01L21/265 , H01L29/00 , H01L29/76 , H01L29/78
CPC分类号： H01L29/00 , H01L21/00 , H01L21/265 , H01L29/76
摘要： A metal oxide semiconductor integrated circuit of reduced size and a method for manufacturing same wherein the size reduction results from the elimination of the usual dimensional tolerances on the width of the gate electrode of the transistors therein. Misalignment of the gate electrode along the width of the underlying thin insulating layer of the channel region, which normally causes degraded performance, is compensated for by implanting ions of the same conductivity determining type as the original substrate in the channel region beneath the areas of the thin insulating layer exposed by the misalignment. No additional masking operation is necessary. The implanted ions prevent the formation of an uncontrollable conducting path between the source and drain regions normally caused by this misalignment, thus eliminating the necessity for the use of an oversized gate electrode to insure that exposed areas of the thin insulating layer are not present. The use of smaller gate electrodes substantially reduces the size of the transistors and therefore the entire circuit.
摘要翻译：一种尺寸减小的金属氧化物半导体集成电路及其制造方法，其中尺寸减小是由于消除其中的晶体管的栅电极的宽度上的常规尺寸公差。通常导致性能下降的通道区域的下层薄绝缘层的宽度的栅电极的不对准通过在与该区域的区域下方的沟道区域中的沟道区域中注入与原始衬底相同的导电性确定类型的离子来补偿薄的绝缘层由不对准而暴露。不需要额外的掩蔽操作。注入的离子防止在通常由该未对准引起的源极和漏极区域之间形成不可控制的导电路径，从而消除了使用过大栅电极以确保薄绝缘层的暴露区域不存在的必要性。使用较小的栅电极大大减小了晶体管的尺寸，并因此大大减小了整个电路。

4. 发明授权

US3882472A Data flow control in memory having two device memory cells 失效
标题翻译：具有两个器件存储单元的存储器中的数据流控制
公开(公告)号：US3882472A
公开(公告)日：1975-05-06
申请号：US47439174
申请日：1974-05-30
申请人： GEN INSTRUMENT CORP
发明人： SMITH KENT F
IPC分类号： G11C11/403 , G11C11/404 , G11C11/24 , G11C7/00 , G11C11/40
CPC分类号： G11C11/403 , G11C11/404
摘要： Method and apparatus for controlling data flow in a memory comprised of a two device memory cell wherein the devices in the cell are connected through a storage node. A first command line is operably connected to the control terminal of the first device in the cell and the output circuit of the first device is connected between a data input-output line and the storage node. The second device in the cell has its output circuit connected between the data line and a second command line and its control terminal connected to the storage node. The storage node is charged to one of two discrete logic levels. To perform a read operation, the data line is precharged to a first voltage level and the second command line is precharged to a first voltage voltage level. The second device in the cell is effective, if rendered conductive by the charge on the storage node, to change the voltage level of the data line to the second voltage level such that the resulting voltage level on the data line is representative of the charge on the storage node, and therefore the data in the cell, which may then be read. In order to write data into the cell, the data line is charged to a voltage level representative of the data to be stored (which may be the resulting voltage if refreshing is to take place) and the first command line is charged to a first voltage level such that the first device is rendered conductive to charge the storage node to the voltage level present on the data line. A combination of a read cycle and a write cycle refreshes the cell without the necessity of a refresh amplifier.

5. 发明授权

US3868274A Method for fabricating MOS devices with a multiplicity of thresholds on a semiconductor substrate 失效
标题翻译：一种在半导体衬底上制造具有多个阈值的MOS器件的方法
公开(公告)号：US3868274A
公开(公告)日：1975-02-25
申请号：US43002574
申请日：1974-01-02
申请人： GEN INSTRUMENT CORP
发明人： HUBAR ROBERT J , SMITH KENT F , FORDEMWALT JAMES N , HANSON JOHN W
IPC分类号： H01L21/8234 , H01L21/265 , H01L21/336 , H01L21/8247 , H01L27/06 , H01L27/088 , H01L29/00 , H01L29/78 , H01L29/788 , H01L29/792 , H01L7/00
CPC分类号： H01L27/0883 , H01L27/088 , H01L29/00 , Y10S148/018 , Y10S148/053
摘要： The process includes the steps of doping selected portions of the substrate with a dopant of conductivity-determining type opposite the conductivity type of the substrate to form source and drain regions for a plurality of semiconductor devices. A first conductivity-determining type impurity is then introduced into the substrate at the surface thereof in regions corresponding to a first set of selected devices and not in regions corresponding to a second set of selected devices. A second conductivity type determining impurity is then introduced into the substrate of the surface thereof in regions corresponding to the second set of selected devices. The second conductivity type determining impurity is also introduced in regions corresponding to at least some of the first set of selected devices. There may be a third set of selected devices where neither of the conductivity type determining impurities are introduced. The source, drain and gate electrodes for each devices are then formed. Preferably, the introduction of the conductivity type determining impurities is achieved by means of ion implantation. The resulting substrate may have devices having as many as four different threshold voltages depending upon which, if any, of the impurities are implanted in the channel regions of the particular devices. By controlling the relative impurity concentrations, the threshold voltages of the devices may be accurately determined. Further, the implantation procedures perform the additional function of doping the field areas to substantially reduce parasitic transistor action between the devices caused by field inversion.
摘要翻译：该方法包括以下步骤：用与衬底的导电类型相反的导电性确定类型的掺杂剂掺杂衬底的选定部分，以形成用于多个半导体器件的源极和漏极区域。然后在对应于第一组选定器件的区域的表面上将第一导电率确定型杂质引入衬底中，而不是在与第二组选定器件相对应的区域中。然后在对应于第二组选定器件的区域中将第二导电类型确定杂质引入其表面的衬底中。第二导电类型确定杂质也被引入到与第一组选定器件中的至少一些对应的区域中。可能存在导入类型不确定杂质的第三组选定装置。然后形成每个器件的源极，漏极和栅电极。

6. 发明授权

US3683203A Electronic shift register system 失效
标题翻译：电子移位寄存器系统
公开(公告)号：US3683203A
公开(公告)日：1972-08-08
申请号：US3683203D
申请日：1969-09-08
申请人： GEN INSTRUMENT CORP
发明人： SMITH KENT F
IPC分类号： G11C19/28 , G11C19/18 , H03K19/096 , G11C19/00
CPC分类号： G11C19/184
摘要： A controlled, regenerative, feedback is utilized to connect the output potential of a data input transfer stage of a shift register circuit to the control terminal of an output transfer stage of a preceeding shift register circuit that is connected therewith in series. The feedback permits control by expanded pulses of indefinite time length and any polarity, thereby greatly increasing the usefulness of such shift registers. With this arrangement the manufacture and use of identical, singlestage circuit modules that may be connected in series for greater flexibility in designing electronic shift register systems is greatly simplified.
摘要翻译：使用受控的再生的反馈来将移位寄存器电路的数据输入传送级的输出电位连接到与其串联连接的先前的移位寄存器电路的输出传输级的控制端。反馈允许通过不确定时间长度和任何极性的扩展脉冲进行控制，从而大大增加这种移位寄存器的有用性。通过这种布置，可以大大简化在设计电子移位寄存器系统时串联连接的相同的单级电路模块的制造和使用以获得更大的灵活性。

7. 发明授权

US3657557A Synchronous binary counter 失效
标题翻译：同步二进制计数器
公开(公告)号：US3657557A
公开(公告)日：1972-04-18
申请号：US3657557D
申请日：1970-10-19
申请人： GEN INSTRUMENT CORP
发明人： SMITH KENT F , WANLASS FRANK M
IPC分类号： H03K23/00 , H03K23/22
CPC分类号： H03K23/001
摘要： A multistage synchronous binary counter has an improved high speed carry means which is responsive only to the previous stage. Each stage comprises three inverters connected in series, the first and second inverters being isolated periodically by a clocked switching device. Two feedback paths in each stage comprising two switching devices each are adapted to feed back the signals at the outputs of the second and third inverters respectively to the input node, the control terminals of said switching devices being connected to selected nodes in the preceding stage. Another clocked switching device is interposed in both feedback paths whereby each count takes place over a period defined by first and second nonoverlapping clock signals applied to the first and second clocked switching devices, respectively.
摘要翻译：多级同步二进制计数器具有改进的高速进位装置，其仅响应于前一级。每个级包括串联连接的三个反相器，第一和第二反相器被定时开关器件周期性隔离。包括两个开关装置的每个级中的两个反馈路径分别适于将第二和第三反相器的输出端的信号反馈到输入节点，所述开关装置的控制端在前一级连接到选定的节点。另一个时钟切换装置插入在两个反馈路径中，由此每个计数分别在由施加到第一和第二时钟控制的开关装置的第一和第二非重叠时钟信号限定的时段内进行。

8. 发明授权

US3621387A Computer-controlled tester for integrated circuit devices 失效
标题翻译：用于集成电路设备的计算机控制测试仪
公开(公告)号：US3621387A
公开(公告)日：1971-11-16
申请号：US3621387D
申请日：1969-08-21
申请人： GEN INSTRUMENT CORP
发明人： SMITH KENT F , SMITH KAY D
IPC分类号： G01R31/26 , G01R31/3193 , G01R31/00
CPC分类号： G01R31/2644 , G01R31/2607 , G01R31/3193
摘要： A test apparatus produces a simulated input signal for a device under test and a predicted output signal which that device would correctly product at its output in response to that simulated input. The device output signal and the predicted output signal are compared for logic content, and the amplitude of the device output signal is compared against predetermined reference levels. A separate error signal is produced upon the occurrence of an error in either of these properties in the device output signal. The input and predicted output signals are initially stored into the apparatus from an external computer which also establishes the appropriate clock signals and power supply signals for the device under test. In the embodiment herein shown, the input and output data is preloaded in shift registers and means are provided to sequentially transfer the simulated input and predicted output signals in a time controlled manner from these shift registers to the device and to the output signal comparator.

9. 发明专利

CA1011005A METHOD FOR FABRICATING MOS DEVICES WITH A MULTIPLICITY OF THRESHOLDS ON A SINGLE SEMICONDUCTOR TRATE 未知
公开(公告)号：CA1011005A
公开(公告)日：1977-05-24
申请号：CA216738
申请日：1974-12-23
申请人： GEN INSTRUMENT CORP
发明人： HUBER ROBERT J , SMITH KENT F , FORDEMWALT JAMES N , HANSON JOHN W
IPC分类号： H01L21/8234 , H01L21/265 , H01L21/336 , H01L21/8247 , H01L27/06 , H01L27/088 , H01L29/00 , H01L29/78 , H01L29/788 , H01L29/792

10. 发明专利

GB2149989A Data storage cell 未知
公开(公告)号：GB2149989A
公开(公告)日：1985-06-19
申请号：GB8430492
申请日：1984-12-03
申请人： GEN INSTRUMENT CORP
发明人： KNAPP WILLIAM , DUNN WILLIAM , SMITH KENT F
IPC分类号： G11C7/00 , H03K19/177 , H03K19/00
摘要： A storage cell 28 has separate means for reading data in (507, 539) and out (509, 535). The cell may be used in a clocked storage logic array formed from a plurality of columns (25, 35) and a plurality of rows (26, 27, 29) disposed orthogonal to the columns. Logic cells (21 etc) interconnect selected columns and rows. Storage cells (28) are operatively associated with some of the columns in the array, known as data columns (25). Each storage cell (28 or) utilizes only two column conductors (20, 22) which are time shared to provide a data path from a memory element in the storage cell to a specified row or rows and back from the row(s) through the same column conductors to the memory. A plurality of phase-displaced clock periods ( phi 1- phi 4) operate in association with the storage cells to enable the two column conductors to each storage cell to be time shared and also cooperate with logic cells to cause selected rows to assume binary states determined by the binary state of interconnected columns, and vice-versa.

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