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1. 发明授权

US6040995A Method of operating a storage cell arrangement 失效
标题翻译：操作存储单元布置的方法
公开(公告)号：US6040995A
公开(公告)日：2000-03-21
申请号：US230614
申请日：1999-01-28
申请人： Hans Reisinger , Ulrike Gruning , Hermann Wendt , Reinhard Stengl , Volker Lehmann , Josef Willer , Martin Franosch , Herbert Schafer , Wolfgang Krautschneider , Franz Hofmann , Thomas Bohm
发明人： Hans Reisinger , Ulrike Gruning , Hermann Wendt , Reinhard Stengl , Volker Lehmann , Josef Willer , Martin Franosch , Herbert Schafer , Wolfgang Krautschneider , Franz Hofmann , Thomas Bohm
IPC分类号： H01L21/8247 , H01L29/51 , H01L29/788 , H01L29/792 , H01L27/02
CPC分类号： H01L29/513 , H01L29/518 , H01L29/792
摘要： For the operation of a memory cell arrangement with MOS transistors as memory cells that comprise a dielectric triple layer (5) with a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53) as gate dielectric, whereby the silicon oxide layers are respectively at least 3 nm thick, a first cutoff voltage value is allocated to a first logical value and a second cutoff voltage value of the MOS transistor is allocated to a second logical value for storing digital data. The information stored in the memory cell can be modified by applying corresponding voltage levels, although a complete removal of charge stored in the silicon nitride layer is not possible because of the thickness of the silicon oxide layers. What is exploited when modifying the cutoff voltage is that the electrical field in the dielectric triple layer is distorted by charge stored in the silicon nitride layer.
摘要翻译： PCT No.PCT / DE97 / 01601 Sec。 371日期1999年1月28日 102（e）1999年1月28日PCT PCT 1997年7月29日PCT公布。出版物WO98 / 06140 日期1998年2月12日对于具有MOS晶体管的存储单元布置的操作，作为包含具有第一氧化硅层（51）的介电三层（5）的存储单元，具有氮化硅层（52）和第二氧化硅层（53）作为栅极电介质，由此氧化硅层分别为至少3nm厚，将第一截止电压值分配给第一逻辑值，并将MOS晶体管的第二截止电压值分配给第二逻辑值用于存储数字数据。存储在存储单元中的信息可以通过施加相应的电压电平来修改，尽管由于氧化硅层的厚度，不可能完全去除存储在氮化硅层中的电荷。当修改截止电压时，利用的是电介质三层中的电场由存储在氮化硅层中的电荷而失真。

2. 发明授权

US5882969A Method for manufacturing an electrically writeable and erasable read-only memory cell arrangement 失效
标题翻译：用于制造电可写和可擦除的只读存储单元布置的方法
公开(公告)号：US5882969A
公开(公告)日：1999-03-16
申请号：US967419
申请日：1997-11-11
申请人： Wolfgang Krautschneider , Franz Hofmann , Hans Reisinger , Josef Willer
发明人： Wolfgang Krautschneider , Franz Hofmann , Hans Reisinger , Josef Willer
IPC分类号： H01L21/822 , H01L21/8247 , H01L29/788 , H01L29/792 , H01L21/336 , H01L29/78
CPC分类号： H01L27/11521 , H01L21/8221 , H01L27/11551
摘要： In a method for manufacturing an electrically writeable and erasable ad-only memory cell arrangement, by self-adjusting process steps, a read-only memory cell arrangement having memory cells that respectively comprise an MOS transistor with a floating gate is manufactured. The MOS transistors are arranged in rows that run parallel. Adjacent rows thus respectively run alternately on the bottom of longitudinal trenches and between adjacent longitudinal trenches. The control gates laterally surround the floating gates so that the memory cells on the bottom of the longitudinal trenches also comprise a coupling ratio>1. A surface requirement per memory cell of 2F.sup.2 (F minimum structural size) is achieved.
摘要翻译：在通过自调整处理步骤制造电可写和可擦除的仅ad的存储单元布置的方法中，制造了具有分别包括具有浮置栅极的MOS晶体管的存储单元的只读存储单元布置。 MOS晶体管排列成并行的行。因此，相邻的行分别在纵向沟槽的底部和相邻的纵向沟槽之间交替地行进。控制门横向围绕浮动栅极，使得纵向沟槽底部的存储单元也包括耦合比> 1。实现2F2（F最小结构尺寸）每个存储单元的表面要求。

3. 发明授权

US5744393A Method for production of a read-only-memory cell arrangement having vertical MOS transistors 失效
标题翻译：用于制造具有垂直MOS晶体管的只读存储单元布置方法
公开(公告)号：US5744393A
公开(公告)日：1998-04-28
申请号：US836175
申请日：1997-04-17
申请人： Lothar Risch , Franz Hofmann , Wolfgang Rosner , Wolfgang Krautschneider
发明人： Lothar Risch , Franz Hofmann , Wolfgang Rosner , Wolfgang Krautschneider
IPC分类号： H01L21/8234 , H01L21/8246 , H01L27/088 , H01L27/112 , H01L29/739 , H01L29/78
CPC分类号： H01L27/112
摘要： A method for production of a read-only-memory cell arrangement having vertical MOS transistors is provided. In order to produce a read-only-memory cell arrangement which has first memory cells having a vertical MOS transistor and second memory cells which do not have a vertical MOS transistor, holes provided with a gate dielectric and a gate electrode are etched in a silicon substrate with a layer sequencing corresponding to a source, a channel and a drain for the first memory cells. Insulation trenches whose separation is preferably equal to their width are produced for insulation of adjacent memory cells.
摘要翻译： PCT No.PCT / DE95 / 01365 Sec。 371日期1997年04月17日 102（e）日期1997年4月17日PCT提交1995年10月5日PCT公布。出版物WO96 / 13064 日期：1996年5月2日提供具有垂直MOS晶体管的只读存储单元布置方法。为了产生具有垂直MOS晶体管的第一存储单元和不具有垂直MOS晶体管的第二存储单元的只读存储单元布置，在栅极电介质和栅电极中设置的孔被蚀刻在硅具有对应于第一存储器单元的源极，沟道和漏极的层序列的衬底。为了绝缘相邻的存储单元而产生绝缘沟槽，其隔离优选等于其宽度。

4. 发明授权

US06593614B1 Integrated circuit configuration having at least one transistor and one capacitor, and method for fabricating it 有权
标题翻译：具有至少一个晶体管和一个电容器的集成电路配置及其制造方法
公开(公告)号：US06593614B1
公开(公告)日：2003-07-15
申请号：US09716336
申请日：2000-11-20
申请人： Franz Hofmann , Wolfgang Krautschneider
发明人： Franz Hofmann , Wolfgang Krautschneider
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L27/10808 , H01L27/10823 , H01L27/10876
摘要： A patterned conductive layer and a structure via which a transistor can be driven, e.g. a word line, are disposed one above the other. A vertical conductive structure, e.g. a spacer, connects a first source/drain region of the transistor to the conductive layer, with which it forms a first capacitor electrode which has a large effective area in conjunction with a high packing density. A capacitor dielectric is disposed over the vertical conductive structure and the conductive layer, and a second capacitor electrode is disposed over the capacitor dielectric. The vertical conductive structure may be disposed on a first sidewall of the first source/drain region and a gate electrode of the transistor may be disposed on an adjoining second sidewall of the first source/drain region. The circuit configuration may form a DRAM cell configuration.
摘要翻译：图案化的导电层和可以驱动晶体管的结构，例如，一个字线，一个在另一个之上。垂直导电结构，例如间隔件将晶体管的第一源极/漏极区域连接到导电层，由此形成第一电容器电极，其具有大的有效面积并结合高的堆积密度。电容器电介质设置在垂直导电结构和导电层之上，并且第二电容器电极设置在电容器电介质上。垂直导电结构可以设置在第一源极/漏极区域的第一侧壁上，并且晶体管的栅电极可以设置在第一源极/漏极区域的相邻的第二侧壁上。电路配置可以形成DRAM单元配置。

5. 发明授权

US06518628B1 Integrated CMOS circuit configuration, and production of same 有权
标题翻译：集成CMOS电路配置，生产相同
公开(公告)号：US06518628B1
公开(公告)日：2003-02-11
申请号：US09423864
申请日：1999-11-15
申请人： Wolfgang Krautschneider , Franz Hofmann , Lothar Risch
发明人： Wolfgang Krautschneider , Franz Hofmann , Lothar Risch
IPC分类号： H01L2976
CPC分类号： H01L27/0922
摘要： An integrated CMOS circuit arrangement and a method of manufacturing same, which includes both a first MOS transistor and a second MOS transistor complementary thereto, wherein one of the MOS transistors is arranged at the floor of a trench and the other is arranged at the principal surface of a semiconductor substrate. The MOS transistors are arranged relative to one another such that a current flow through the MOS transistors respectively occurs substantially parallel to a sidewall of the trench that is arranged between the MOS transistors.
摘要翻译：一种集成CMOS电路装置及其制造方法，其包括第一MOS晶体管和与其互补的第二MOS晶体管，其中MOS晶体管中的一个布置在沟槽的底部，而另一个布置在主表面的半导体衬底。 MOS晶体管相对于彼此布置，使得流过MOS晶体管的电流分别基本上平行于布置在MOS晶体管之间的沟槽的侧壁。

6. 发明授权

US6125050A Configuration for driving parallel lines in a memory cell configuration 有权
标题翻译：用于驱动存储单元配置中的并行线的配置
公开(公告)号：US6125050A
公开(公告)日：2000-09-26
申请号：US335365
申请日：1999-06-17
申请人： Franz Hofmann , Josef Willer , Hans Reisinger , Paul-Werner Basse , Wolfgang Krautschneider
发明人： Franz Hofmann , Josef Willer , Hans Reisinger , Paul-Werner Basse , Wolfgang Krautschneider
IPC分类号： H01L27/112 , G11C5/02 , H01L21/8246
CPC分类号： H01L27/0207 , H01L27/1126 , H01L27/11293 , H01L27/11803
摘要： Parallel lines, for example bit lines in a memory cell configuration formed of doped regions in a semiconductor substrate, are driven by electrically connecting a number of the lines to one another and to a common node. A number of selection lines extend transversely to the lines. MOS transistors are arranged at the points of intersection and are connected in series along one of the lines. The gate electrode of the MOS transistors is formed by the corresponding selection line. At least one MOS transistor in each of the parallel lines has a higher threshold voltage than the others.
摘要翻译：平行线，例如由半导体衬底中的掺杂区形成的存储单元配置中的位线，通过将多个线彼此电连接并连接到公共节点来驱动。多条选择线横向延伸。 MOS晶体管布置在交点处，并沿着一条线串联连接。 MOS晶体管的栅电极由相应的选择线形成。每条并行线路中的至少一个MOS晶体管的阈值电压高于其他。

7. 发明授权

US06475866B2 Method for production of a memory cell arrangement 失效
标题翻译：存储单元布置的制造方法
公开(公告)号：US06475866B2
公开(公告)日：2002-11-05
申请号：US09774316
申请日：2001-01-31
申请人： Franz Hofmann , Wolfgang Krautschneider , Josef Willer
发明人： Franz Hofmann , Wolfgang Krautschneider , Josef Willer
IPC分类号： H01L21336
CPC分类号： H01L27/112 , G11C11/5692 , H01L27/11273
摘要： A method for production of a memory cell arrangement which includes vertical MOS transistors as memory cells, wherein the information is stored utilizing at least three different threshold voltage values of the transistors by multi-level programming. One threshold voltage value is realised by the thickness of the gate dielectric in the sense of a thick oxide transistor and the other threshold voltage values are realised by different channel dopings. The arrangement can be produced with as area requirement for each memory cell of 2 F2 (F: minimum structure size).
摘要翻译：一种用于生产包括垂直MOS晶体管作为存储单元的存储单元布置的方法，其中通过多级编程利用晶体管的至少三个不同阈值电压值存储信息。通过厚氧化物晶体管的意义上的栅极电介质的厚度实现一个阈值电压值，并且通过不同的沟道掺杂实现其它阈值电压值。可以按照2 F2（F：最小结构尺寸）的每个存储单元的面积要求来生成该布置。

8. 发明授权

US06445046B1 Memory cell arrangement and process for manufacturing the same 失效
标题翻译：存储单元布置及其制造方法
公开(公告)号：US06445046B1
公开(公告)日：2002-09-03
申请号：US09331034
申请日：1999-06-15
申请人： Franz Hofmann , Josef Willer , Hans Reisinger , Paul Werner von Basse , Wolfgang Krautschneider
发明人： Franz Hofmann , Josef Willer , Hans Reisinger , Paul Werner von Basse , Wolfgang Krautschneider
IPC分类号： H01L29772
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L27/11517
摘要： A number of memory cell lines insulated from one another and that respectively comprise a first doped region and a second doped region between which a gate dielectric, which contains a material with charge carrier traps and a number of gate electrodes. The spacing of neighboring gate electrodes is smaller than the dimensions of the gate electrodes. The information is stored by introduction of charge carriers into the gate dielectric. The gate electrodes are preferably manufactured with the assistance of a spacer technique.
摘要翻译：多个彼此绝缘的存储器单元线路，并且分别包括第一掺杂区域和第二掺杂区域，在该第二掺杂区域和第二掺杂区域之间包含具有电荷载流子阱的材料和多个栅电极的栅极电介质。相邻栅电极的间隔小于栅电极的尺寸。通过将电荷载体引入栅极电介质来存储信息。优选地，通过间隔物技术来制造栅电极。

9. 发明授权

US06438022B2 Memory cell configuration 失效
标题翻译：内存单元配置
公开(公告)号：US06438022B2
公开(公告)日：2002-08-20
申请号：US09854259
申请日：2001-05-10
申请人： Till Schlösser , Wolfgang Krautschneider , Franz Hofmann , Thomas-Peter Haneder
发明人： Till Schlösser , Wolfgang Krautschneider , Franz Hofmann , Thomas-Peter Haneder
IPC分类号： G11C1122
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/11507
摘要： The memory cells of a memory cell configuration each have a selection transistor, a memory transistor and a ferroelectric capacitor. The selection transistor and the memory transistor are connected in series. The ferroelectric capacitor is connected between a control electrode of the memory transistor and a first terminal of the selection transistor.
摘要翻译：存储单元结构的存储单元分别具有选择晶体管，存储晶体管和铁电电容器。选择晶体管和存储晶体管串联连接。铁电电容器连接在存储晶体管的控制电极和选择晶体管的第一端子之间。

10. 发明授权

US06399433B2 Method for fabricating a memory cell 有权
标题翻译：用于制造存储单元的方法
公开(公告)号：US06399433B2
公开(公告)日：2002-06-04
申请号：US09773218
申请日：2001-01-31
申请人： Franz Hofmann , Wolfgang Krautschneider , Till Schlösser , Josef Willer
发明人： Franz Hofmann , Wolfgang Krautschneider , Till Schlösser , Josef Willer
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/55
摘要： A method for producing a storage cell includes forming a polycrystalline silicon layer on a semiconductor body having at least one selection transistor disposed in a first plane. An interspace is formed between two adjacent structures of the layer and one of the adjacent structures of the layer is placed on a surface of a first silicon plug. A cell plate electrode is formed in the interspace and a trench is formed in the layer. The trench reaches as far as the first plug surface and is filled with an insulating layer. The-layer is removed. A storage capacitor having a high-epsilon or ferroelectric dielectric and a storage node electrode is formed. The capacitor is disposed in a second plane in and above the body. The insulating layer is replaced with silicon to form a second silicon plug directly connected to the first plug. The second plug is electrically connected to the storage node electrode, and the first plane is electrically connected to the second plane through the first and second plugs.
摘要翻译：一种存储单元的制造方法包括在半导体本体上形成多晶硅层，该多晶硅层具有设置在第一平面中的至少一个选择晶体管。在层的两个相邻结构之间形成间隙，并且该层的相邻结构之一被放置在第一硅插头的表面上。在该间隙中形成单元板电极，并在该层中形成沟槽。沟槽达到第一插头表面的最远处，并且填充有绝缘层。该层被删除。形成具有高ε或铁电介质的存储电容器和存储节点电极。电容器设置在身体内和上方的第二平面内。绝缘层被硅替代以形成直接连接到第一插头的第二硅插头。第二插头电连接到存储节点电极，第一平面通过第一和第二插头电连接到第二平面。

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