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1. 发明授权

US5113259A Data transfer from an external computer to a television receiver having picture-in-picture capability 失效
标题翻译：从外部计算机到具有画中画能力的电视接收机的数据传输
公开(公告)号：US5113259A
公开(公告)日：1992-05-12
申请号：US511269
申请日：1990-04-19
申请人： Eric D. Romesburg , Kenneth W. Maze , David J. Duffield , Michael S. Deiss , Billy W. Beyers, Jr. , Kevin E. Bridgewater
发明人： Eric D. Romesburg , Kenneth W. Maze , David J. Duffield , Michael S. Deiss , Billy W. Beyers, Jr. , Kevin E. Bridgewater
IPC分类号： H04N5/265 , H04N5/45
CPC分类号： H04N5/45
摘要： The digitized video image data stored in a video RAM in a pix-in-pix television receiver is modified by the addition of digital data from an external computer via a computer interface circuit under control of the pix-in-pix controller. The computer interface circuit is coupled to the internal controller of the television receiver via an external input terminal. The additional digital data received from the external computer may be representative of either text or graphics to be merged into the stored video image.
摘要翻译：通过在pix-in-pix控制器的控制下经由计算机接口电路从外部计算机添加数字数据来修改存储在pix-in-pix电视接收机中的视频RAM中的数字化视频图像数据。计算机接口电路通过外部输入端子耦合到电视接收机的内部控制器。从外部计算机接收的附加数字数据可以代表要合并到存储的视频图像中的文本或图形。

2. 发明授权

US5111296A Data transfer from a television receiver having picture-in-picture capability to an external computer 失效
标题翻译：从具有画中画能力的电视接收机向外部计算机传送数据
公开(公告)号：US5111296A
公开(公告)日：1992-05-05
申请号：US510711
申请日：1990-04-19
申请人： David J. Duffield , Michael S. Deiss , Billy W. Beyers, Jr. , Kevin E. Bridgewater
发明人： David J. Duffield , Michael S. Deiss , Billy W. Beyers, Jr. , Kevin E. Bridgewater
IPC分类号： G06F3/00 , H04N5/45
CPC分类号： G06F3/002 , H04N5/45
摘要： The stored digitized video image data stored in a video RAM is transferred from the video RAM in a pix-in-pix television receiver to an external computer via a computer interface circuit under control of the pix-in-pix controller. The computer interface circuit is coupled to the internal controller of the television receiver via an external terminal. The external terminal receives digital control data from the external computer and conveys the stored digitized video image data signals from the video RAM to the external computer.
摘要翻译：存储在视频RAM中的存储的数字化视频图像数据在像素插入式控制器的控制下，经由计算机接口电路从视频RAM在像素电视接收机中传送到外部计算机。计算机接口电路通过外部端子耦合到电视接收机的内部控制器。外部终端从外部计算机接收数字控制数据，并将存储的数字化视频图像数据信号从视频RAM传送到外部计算机。

3. 发明授权

US06976266B1 Apparatus and method for processing a program guide in a digital video system 失效
标题翻译：用于处理数字视频系统中的节目指南的装置和方法
公开(公告)号：US06976266B1
公开(公告)日：2005-12-13
申请号：US09528507
申请日：2000-03-20
申请人： John W. Chaney , Bill W. Beyers, Jr. , Michael W. Johnson , James E. Hailey , Kevin E. Bridgewater , Michael S. Deiss , Raymond S. Horton
发明人： John W. Chaney , Bill W. Beyers, Jr. , Michael W. Johnson , James E. Hailey , Kevin E. Bridgewater , Michael S. Deiss , Raymond S. Horton
IPC分类号： H04N5/445 , H04N7/16 , H04N7/24 , H04N7/52
CPC分类号： H04N21/435 , H04N5/4401 , H04N5/44543 , H04N21/235 , H04N21/23614 , H04N21/26283 , H04N21/4348 , H04N21/482 , H04N21/4821 , H04N21/84
摘要： A method and an apparatus for processing packetized signal having a plurality of channels carrying program information. The packetized signal also includes program guide information that includes channel identifier data. The program guide information comprises a sequence of data blocks including a segment map that includes information about the partitioning of the plurality of channels into segments and map block that includes information relating specific channels of the plurality of channels with respective channel identifier data.
摘要翻译：一种用于处理分组化信号的方法和装置，其具有携带节目信息的多个频道。分组信号还包括包括频道标识符数据的节目指南信息。节目指南信息包括数据块序列，其包括包括关于将多个频道划分成段的信息的分段映射和包括与多个频道的特定频道相关联的信息的各个频道标识符数据的地图块。

4. 发明授权

US5475754A Packet video signal inverse transport processor memory address circuitry 失效
标题翻译：分组视频信号逆传输处理器存储器地址电路
公开(公告)号：US5475754A
公开(公告)日：1995-12-12
申请号：US232787
申请日：1994-04-22
申请人： Kevin E. Bridgewater , Michael S. Deiss
发明人： Kevin E. Bridgewater , Michael S. Deiss
IPC分类号： H04N7/16 , H04N21/426 , H04N21/434 , H04N7/167
CPC分类号： H04N21/426 , H04N21/434 , H04N7/163
摘要： In an inverse transport processor, program component packet payloads of respective program components are directed to select areas of random access memory (RAM) (18) in accordance with a plurality of start and end pointers which are stored in a first plurality (86, 89) of registers, one for each program component. Addresses are generated, in part, by a plurality of read pointer registers (82) multiplexed with an adder (80) to successively increment the pointers for respective program components. The start pointers are associated with read pointers to from memory addresses that scroll through designated memory blocks selectively assigned to respective program components. Memory access for read and write functions are arbitrated (98) so that no incoming program data can be lost, and all component processors are serviced.
摘要翻译：在反向传输处理器中，根据存储在第一多个（86,89）中的多个开始和结束指针，相应程序组件的程序组件分组有效载荷指向随机存取存储器（RAM）（18）的选择区域）寄存器，每个程序组件一个。部分地由与加法器（80）多路复用的多个读指针寄存器（82）产生地址，以连续递增各个程序组件的指针。起始指针与从选择性分配给相应程序组件的指定存储器块滚动的存储器地址的读指针相关联。对于读写功能的存储器访问（98）进行仲裁，以便不会丢失传入的程序数据，并且对所有组件处理器进行维修。

5. 发明授权

US6064378A Program guide in a digital video system 有权
标题翻译：数字视频系统中的节目指南
公开(公告)号：US6064378A
公开(公告)日：2000-05-16
申请号：US176567
申请日：1998-10-21
申请人： John W. Chaney , Bill W. Beyers, Jr. , Michael W. Johnson , James E. Hailey , Kevin E. Bridgewater , Michael S. Deiss , Raymond S. Horton
发明人： John W. Chaney , Bill W. Beyers, Jr. , Michael W. Johnson , James E. Hailey , Kevin E. Bridgewater , Michael S. Deiss , Raymond S. Horton
IPC分类号： H04N5/445 , H04N5/50
CPC分类号： H04N21/84 , H04N21/435 , H04N21/4382 , H04N5/44543
摘要： Apparatus and method for acquiring a program from a packetized signal in response to ancillary information included in the packetized signal. The packetized signal includes a plurality of program signals and ancillary information associated with the plurality of program signals. The apparatus includes means for identifying the ancillary information from the packetized signal, the ancillary information including master guide information for use in identifying and acquiring special guide information, and special guide information for use in acquiring program information associated with the plurality of program signals. The program signals may be acquired using identifier information that may be derived from the ancillary information. The apparatus includes means responsive to the ancillary information for acquiring a selected program from the packetized signal.
摘要翻译：响应于分组化信号中所包括的辅助信息，从打包信号获取节目的装置和方法。打包信号包括与多个节目信号相关联的多个节目信号和辅助信息。该装置包括用于从分组化信号识别辅助信息的装置，辅助信息包括用于识别和获取特殊指导信息的主指导信息，以及用于获取与多个节目信号相关联的节目信息的特殊指南信息。可以使用可以从辅助信息导出的标识符信息来获取节目信号。该装置包括响应于辅助信息的装置，用于从打包信号获取所选择的节目。

6. 发明授权

US5613003A Packet video signal inverse transport processor memory address circuitry 失效
标题翻译：分组视频信号逆传输处理器存储器地址电路
公开(公告)号：US5613003A
公开(公告)日：1997-03-18
申请号：US527663
申请日：1995-09-13
申请人： Kevin E. Bridgewater , Michael S. Deiss
发明人： Kevin E. Bridgewater , Michael S. Deiss
IPC分类号： H04N7/16 , H04N21/426 , H04N21/434 , H04N7/167
CPC分类号： H04N21/426 , H04N21/434 , H04N7/163
摘要： In an inverse transport processor, program component packet payloads of respective program components are multiplexed to a memory data input port and directed to mutually exclusive areas of random access memory (RAM). The processor includes multiple direct memory access circuitry for writing the payloads of component data to the mutually exclusive blocks of the memory. Memory access for read and write functions are arbitrated so that no incoming program data can be lost, and all component processors are serviced.
摘要翻译：在逆传输处理器中，各个节目组件的节目分量分组有效载荷被多路复用到存储器数据输入端口并指向随机存取存储器（RAM）的互斥区域。处理器包括多个直接存储器访问电路，用于将组件数据的有效载荷写入存储器的互斥块。对读和写功能的存储器访问进行仲裁，以便不会丢失传入的程序数据，并且对所有组件处理器进行维修。

7. 发明授权

US5475688A Media error code generation as for a video inverse transport processor 失效
标题翻译：视频反向传输处理器的媒体错误代码生成
公开(公告)号：US5475688A
公开(公告)日：1995-12-12
申请号：US232932
申请日：1994-04-22
申请人： Kevin E. Bridgewater , Michael S. Deiss , Gregory G. Tamer
发明人： Kevin E. Bridgewater , Michael S. Deiss , Gregory G. Tamer
IPC分类号： H04L12/70 , H04L12/951 , H04N5/44 , H04N7/015 , H04N19/60 , H04N19/89 , H04J3/26
CPC分类号： H04N5/4401 , H04N19/89 , H04N21/4385 , H04N21/44209 , H04N21/4181 , H04N21/43853
摘要： In an inverse transport processor of the type which directs video payloads of a packet signal to buffer memory space, apparatus is included for writing a media error codes at sequential first memory address locations in the memory ahead of each packet payload. Concurrently a processor examines the current packet to determine if it occurs in proper sequence. If a packet is lost, the payload is written to memory in subsequent sequential address locations. If there is no packet loss, the sequential first memory address locations are simply overwritten by the packet payload to excise the undesired media error code. Media error codes can thus be inserted in the packet payload stream without creating timing obstacles, for a system designer.
摘要翻译：在将分组信号的视频有效载荷引导到缓冲存储器空间的逆传输处理器中，包括用于在每个分组有效载荷之前的存储器中的连续的第一存储器地址位置处写入介质错误代码的装置。同时处理器检查当前数据包，以确定它是否以正确的顺序发生。如果数据包丢失，则有效载荷将在随后的顺序地址位置写入存储器。如果没有分组丢失，则顺序的第一存储器地址位置被分组有效载荷简单地覆盖以消除不期望的媒体错误代码。因此，对于系统设计者，媒体错误代码因此可以插入分组有效载荷流中而不产生时序障碍。

8. 发明授权

US5619501A Conditional access filter as for a packet video signal inverse transport system 失效
标题翻译：条件访问过滤器用于分组视频信号反向传输系统
公开(公告)号：US5619501A
公开(公告)日：1997-04-08
申请号：US232794
申请日：1994-04-22
申请人： Gregory G. Tamer , Michael S. Deiss , John W. Chaney , James E. Hailey
发明人： Gregory G. Tamer , Michael S. Deiss , John W. Chaney , James E. Hailey
IPC分类号： H04N5/00 , H04N5/44 , H04N7/16 , H04N7/167 , H04N21/266 , H04N21/418 , H04N21/426 , H04N21/4385 , H04N21/4405 , H04N21/4623 , H04N21/4627 , H04J3/26
CPC分类号： H04N21/42623 , H04N21/26606 , H04N21/4181 , H04N21/4405 , H04N21/4623 , H04N5/4401 , H04N7/163 , H04N7/165 , H04N7/1675
摘要： Apparatus in a receiver, for processing transmitted entitlement control information, includes a packet transport processor for selecting signal packets having payloads containing a conditional access payload header and a remaining payload of entitlement data. Respective payload headers include groups of bytes which are coded in a manner to allow or disallow the respective receiver from processing the entitlement data. A conditional access filter preprogrammed with a subscriber specific conditional access codeword examines respective byte groupings of the conditional access header for a match with the subscriber specific conditional access codeword. Only if a match occurs is the processor permitted to process the entitlement data. The entitlement data is thereafter utilized to generate decryption keys for descrambling portions of the transmitted signal.
摘要翻译：在接收机中用于处理发送的授权控制信息的装置包括分组传输处理器，用于选择具有有效载荷的信号分组，该分组传输处理器包含条件访问有效载荷报头和授权数据的剩余有效载荷。相应的有效负载报头包括以允许或不允许相应的接收机处理授权数据的方式编码的字节组。用用户特定的条件访问代码字预编程的条件访问过滤器检查条件访问头的相应字节分组以与用户特定条件访问代码字匹配。只有匹配发生，才允许处理器处理授权数据。随后利用授权数据产生用于解扰发送信号的部分的解密密钥。

9. 发明授权

US5430485A Audio/video synchronization in a digital transmission system 失效
标题翻译：数字传输系统中的音频/视频同步
公开(公告)号：US5430485A
公开(公告)日：1995-07-04
申请号：US129974
申请日：1993-09-30
申请人： Douglas E. Lankford , Michael S. Deiss
发明人： Douglas E. Lankford , Michael S. Deiss
IPC分类号： H04N5/04 , H04N5/44 , H04N5/60 , H04N7/04 , H04N7/045 , H04N7/08 , H04N7/081 , H04N7/12 , H04N7/26 , H04N7/56 , H04N19/00 , H04N11/02
CPC分类号： H04N21/4305 , H04N21/4307 , H04N21/4392 , H04N5/04 , H04N5/4401 , H04N5/602 , H04N7/56
摘要： A receiver (FIG. 2 ) for decoding associated compressed video and audio information components transmitted in mutually exclusive "frames" of data with respective time stamps PTS.sub.vid and PTS.sub.aud respectively, includes a controller (216) which is responsive to the respective received time stamps to provide coarse synchronization by delaying or skipping respective frames of one or the other of the components to approximately time align the two components. Fine synchronization is provided by adjusting the processing or clock frequency (215) of the audio signal processor (212) independent of the video processor (214). The control for the frequency adjustment is related to the difference between audio and video time stamps.
摘要翻译：用于分别用相应的时间戳PTSvid和PTSaud分别在相互排斥的数据“帧”中传送的相关联的压缩视频和音频信息分量的接收机（图2）包括控制器（216），其响应于相应接收的时间戳通过延迟或跳过一个或另一个组件的相应帧来大致时间对准两个组件来提供粗略的同步。通过独立于视频处理器（214）调整音频信号处理器（212）的处理或时钟频率（215）来提供精细同步。频率调整的控制与音频和视频时间戳的区别有关。

10. 发明授权

US06594361B1 High speed signal processing smart card 失效
标题翻译：高速信号处理智能卡
公开(公告)号：US06594361B1
公开(公告)日：2003-07-15
申请号：US08792816
申请日：1997-01-30
申请人： John William Chaney , Michael S. Deiss , Billy W. Beyers
发明人： John William Chaney , Michael S. Deiss , Billy W. Beyers
IPC分类号： H04N7167
CPC分类号： G07F7/1008 , G06Q20/341 , G06Q20/346 , G06Q20/3578 , G06Q20/40975 , H04N7/163 , H04N7/1675 , H04N21/4181 , H04N21/42623 , H04N21/4405 , H04N21/4623
摘要： An access control system for signal processing applications includes an integrated circuit (IC) card, or “smart” card, that provides both security control and data descrambling functions. A security control processor in the smart card IC performs functions such as entitlement management and key generation. The smart card IC also includes a descrambler for processing data, such as video data, at high data rates. Mechanical characteristics of the smart card satisfy the ISO standard 7816-1. In addition, the interface to the smart card is via eight-terminals arranged on the surface of the card in accordance with ISO standard 7816-2. The eight terminal interface provides both high speed data I/O (input and output) required for data descrambling and ISO standard low speed serial data I/O.
摘要翻译：用于信号处理应用的访问控制系统包括提供安全控制和数据解扰功能的集成电路（IC）卡或“智能”卡。智能卡IC中的安全控制处理器执行诸如授权管理和密钥生成等功能。智能卡IC还包括用于以高数据速率处理诸如视频数据的数据的解扰器。智能卡的机械特性满足ISO标准7816-1。此外，智能卡的接口是根据ISO标准7816-2通过布置在卡表面上的八个端子。八端子接口提供数据解扰所需的高速数据I / O（输入和输出）和ISO标准低速串行数据I / O。

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