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1. 发明授权

US06750095B1 Integrated circuit with vertical transistors 失效
标题翻译：集成电路与垂直晶体管
公开(公告)号：US06750095B1
公开(公告)日：2004-06-15
申请号：US09787966
申请日：2001-05-29
申请人： Emmerich Bertagnoll , Franz Hofmann , Bernd Goebel , Wolfgang Roesner
发明人： Emmerich Bertagnoll , Franz Hofmann , Bernd Goebel , Wolfgang Roesner
IPC分类号： H01L218242
CPC分类号： H01L27/10876 , H01L27/1052 , H01L27/10823 , H01L27/112 , H01L27/11273
摘要： A method of producing an integrated circuit having a vertical MOS transistor includes doping a substrate to form a layer adjacent to its surface and forming a lower doped layer serving as the transistor's first source/drain region. The transistor's channel region is formed by doping a central layer above the lower layer. A second source/drain region is formed by doping an upper layer above the central layer. The upper, central and lower layers form a layer sequence having opposed first and second faces. A connecting structure is formed on the first face to electrically connect the channel region and the substrate. The connecting structure laterally adjoins at least the central layer and the lower layer, and extends into the substrate. A gate dielectric and adjacent gate electrode are formed on the second face.
摘要翻译：制造具有垂直MOS晶体管的集成电路的方法包括：掺杂衬底以形成与其表面相邻的层，并形成用作晶体管的第一源极/漏极区的下掺杂层。晶体管的沟道区域通过在下层上掺杂中心层而形成。通过在中心层上方掺杂上层形成第二源/漏区。上层，中层和下层形成具有相对的第一和第二面的层序列。在第一面上形成连接结构，以电连接沟道区和衬底。连接结构至少横向邻接中心层和下层，并延伸到基底中。在第二面上形成栅电介质和相邻栅电极。

2. 发明授权

US6044009A DRAM cell arrangement and method for its production 有权
标题翻译： DRAM单元布置及其生产方法
公开(公告)号：US6044009A
公开(公告)日：2000-03-28
申请号：US274733
申请日：1999-03-23
申请人： Bernd Goebel , Wolfgang Roesner , Franz Hofmann , Emmerich Bertagnolli , Eve Marie Martin
发明人： Bernd Goebel , Wolfgang Roesner , Franz Hofmann , Emmerich Bertagnolli , Eve Marie Martin
IPC分类号： H01L21/8242 , H01L27/108 , H01L27/04
CPC分类号： H01L27/10876 , H01L27/10808 , H01L27/10823 , Y10S257/906 , Y10S438/947
摘要： A storage cell has a number of projections of a semiconductor substrate arranged in rows and columns, neighboring rows of the projections being translation-symmetrical in relation to a y-axis which extends parallel to the columns. Each of the projections has at least one first source/drain region of a selection transistor and one channel region arranged below the first source/drain region, which is surrounded by a gate electrode annularly. A storage capacitor is connected between the first source/drain region and a bit line. The bit line as well as the storage capacitor are arranged essentially above the semiconductor substrate. Second source/drain regions of selection transistors are buried in the semiconductor substrate and connected with each other. Word lines can be formed self-justified in the form of adjacent gate electrodes. The projections can be created by etching with only one mask. The storage cell can be produced with an area of 4F.sup.2, F being the minimal structural size that can be produced in the respective technology.
摘要翻译：存储单元具有排列成行和列的半导体衬底的多个突起，相邻的一列突起相对于平行于列延伸的y轴平移对称。每个突起具有选择晶体管的至少一个第一源极/漏极区域和布置在第一源极/漏极区域下方的一个沟道区域，其被环形的栅极电极包围。存储电容器连接在第一源极/漏极区域和位线之间。位线以及存储电容器基本上布置在半导体衬底的上方。选择晶体管的第二源极/漏极区域被埋在半导体衬底中并彼此连接。字线可以形成为相邻栅电极的形式自对称。可以通过仅使用一个掩模的蚀刻来产生突起。可以生产具有4F2面积的存储单元，F是可以在各自技术中生产的最小结构尺寸。

3. 发明授权

US06352894B1 Method of forming DRAM cell arrangement 有权
标题翻译：形成DRAM单元布置的方法
公开(公告)号：US06352894B1
公开(公告)日：2002-03-05
申请号：US09482064
申请日：2000-01-13
申请人： Bernd Goebel , Wolfgang Roesner , Franz Hofmann , Emmerich Bertagnolli , Eve Marie Martin
发明人： Bernd Goebel , Wolfgang Roesner , Franz Hofmann , Emmerich Bertagnolli , Eve Marie Martin
IPC分类号： H01L218242
CPC分类号： H01L27/10876 , H01L27/10808 , H01L27/10823 , Y10S257/906 , Y10S438/947
摘要： A storage cell has a number of projections of a semiconductor substrate arranged in rows and columns, neighboring rows of the projections being translation-symmetrical in relation to a y-axis which extends parallel to the columns. Each of the projections has at least one first source/drain region of a selection transistor and one channel region arranged below the first source/drain region, which is surrounded by a gate electrode annularly. A storage capacitor is connected between the first source/drain region and a bit line. The bit line as well as the storage capacitor are arranged essentially above the semiconductor substrate. Second source/drain regions of selection transistors are buried in the semiconductor substrate and connected with each other. Word lines can be formed self-justified in the form of adjacent gate electrodes. The projections can be created by etching with only one mask. The storage cell can be produced with an area of 4F2, F being the minimal structural size that can be produced in the respective technology.
摘要翻译：存储单元具有排列成行和列的半导体衬底的多个突起，相邻的一列突起相对于平行于列延伸的y轴平移对称。每个突起具有选择晶体管的至少一个第一源极/漏极区域和布置在第一源极/漏极区域下方的一个沟道区域，其被环形的栅极电极包围。存储电容器连接在第一源极/漏极区域和位线之间。位线以及存储电容器基本上布置在半导体衬底的上方。选择晶体管的第二源极/漏极区域被埋在半导体衬底中并彼此连接。字线可以形成为相邻栅电极的形式自对称。可以通过仅使用一个掩模的蚀刻来产生突起。可以生产具有4F2面积的存储单元，F是可以在各自技术中生产的最小结构尺寸。

4. 发明申请

US20080035997A1 Fin Field-Effect Transistor and Method for Fabricating a Fin Field-Effect Transistor 审中-公开
标题翻译：翅片场效应晶体管和制造鳍场效应晶体管的方法
公开(公告)号：US20080035997A1
公开(公告)日：2008-02-14
申请号：US11833080
申请日：2007-08-02
申请人： Franz Hofmann , Johannes Kretz , Wolfgang Roesner , Thomas Schulz
发明人： Franz Hofmann , Johannes Kretz , Wolfgang Roesner , Thomas Schulz
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66795
摘要： A fin field-effect transistor has a substrate and a fin structure above the substrate, as well as a drain region and a source region outside the fin structure above the substrate. The fin structure serves as a channel between the source region and the drain region. The source and drain regions are formed once a gate has been produced.
摘要翻译：翅片场效应晶体管具有在衬底上方的衬底和鳍结构，以及在衬底上方的鳍结构之外的漏极区域和源极区域。鳍结构用作源极区域和漏极区域之间的沟道。源极和漏极区域一旦形成栅极就形成。

5. 发明申请

US20050224888A1 Integrated circuit array 审中-公开
标题翻译：集成电路阵列
公开(公告)号：US20050224888A1
公开(公告)日：2005-10-13
申请号：US11116139
申请日：2005-04-27
申请人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Thomas Schulz , Michael Specht
IPC分类号： G11C13/02 , H01L29/78 , H01L51/00 , H01L51/30 , H01L29/76
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/17 , H01L27/283 , H01L51/0048 , H01L51/0052 , H01L51/0512
摘要： Integrated circuit array having field effect transistors (FETs) formed next to and/or above one another. The array has a substrate, a planarized first wiring plane with interconnects and first source/drain regions of the FETs, a planarized first insulator layer on the first wiring plane, a planarized gate region layer, which has patterned gate regions made of electrically conductive material and insulator material introduced therebetween, on the first insulated layer, a planarized second insulator layer on the gate region layer, holes formed through the second insulator layer, the gate regions, and the first insulator layer, a vertical nanoelement serving as a channel region in each of the holes, a second wiring plane with interconnects and second source/drain regions of the FETs, each nanoelement being arranged between the first and second wiring planes, and a gate insulating layer between the respective vertical nanoelement and the electrically conductive material of the gate regions.
摘要翻译：集成电路阵列具有形成在彼此之上和/或彼此之上的场效应晶体管（FET）。阵列具有衬底，具有互连的平坦化的第一布线面和FET的第一源极/漏极区，在第一布线平面上的平坦化的第一绝缘体层，平坦化的栅极区域层，其具有由导电材料制成的图案化栅极区域和介于其间的绝缘体材料，在所述第一绝缘层上，在所述栅极区域层上的平坦化的第二绝缘体层，穿过所述第二绝缘体层，所述栅极区域和所述第一绝缘体层形成的空穴，用作所述沟道区域中的沟道区域的垂直纳米元件每个孔，具有互连的第二布线面和FET的第二源极/漏极区，每个纳米元件布置在第一和第二布线平面之间，并且在相应的垂直纳米元件和导电材料之间的栅极绝缘层门区域。

6. 发明申请

US20050100938A1 Vertical impedance sensor arrangement and method for producing a vertical impedance sensor arrangement 审中-公开
标题翻译：垂直阻抗传感器布置和垂直阻抗传感器布置方法
公开(公告)号：US20050100938A1
公开(公告)日：2005-05-12
申请号：US10939319
申请日：2004-09-09
申请人： Franz Hofmann , Richard Luyken , Wolfgang Roesner
发明人： Franz Hofmann , Richard Luyken , Wolfgang Roesner
IPC分类号： C12Q1/68 , G01N33/543
CPC分类号： G01N33/54386 , G01N27/3276
摘要： Vertical impedance sensor arrangement including a substrate, a first electrically conductive structure having a first uncovered surface and being arranged in and/or on the substrate, a spacer arranged above the substrate and/or at least partially on the first electrically conductive structure, a second electrically conductive structure having a second uncovered surface and being arranged on the spacer, and capture molecules, which are immobilized on the first and on the second uncovered surface, are set up such that particles to be detected hybridize with the capture molecules. The spacer is formed separately from the substrate, and the thickness of the spacer is defined by means of a deposition method.
摘要翻译：垂直阻抗传感器布置包括基底，具有第一未覆盖表面并布置在基底中和/或基底上的第一导电结构，布置在基底上和/或至少部分地在第一导电结构上的间隔物，第二具有第二未覆盖表面并布置在间隔物上的导电结构，并且被固定在第一和第二未覆盖表面上的捕获分子被设置成使得待检测的颗粒与捕获分子杂交。间隔物与衬底分开形成，并且通过沉积方法限定间隔物的厚度。

7. 发明授权

US5821591A High density read only memory cell configuration and method for its production 失效
标题翻译：高密度只读存储单元配置及其生产方法
公开(公告)号：US5821591A
公开(公告)日：1998-10-13
申请号：US794566
申请日：1997-02-03
申请人： Wolfgang Krautschneider , Franz Hofmann , Wolfgang Roesner
发明人： Wolfgang Krautschneider , Franz Hofmann , Wolfgang Roesner
IPC分类号： H01L21/8246 , H01L27/112 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/1128 , H01L27/112
摘要： A memory cell configuration includes first memory cells with planar MOS transistors and second memory cells with vertical MOS transistors. The planar MOS transistors are disposed on the bottom of and on the crown of parallel, strip-like trenches. The vertical MOS transistors are disposed on the side walls of the trenches. The memory cell configuration can be produced with a mean area requirement for each memory cell of 1 F.sup.2, where F is the minimum structure size.
摘要翻译：存储单元配置包括具有平面MOS晶体管的第一存储单元和具有垂直MOS晶体管的第二存储单元。平面MOS晶体管设置在平行的带状沟槽的底部和顶部上。垂直MOS晶体管设置在沟槽的侧壁上。存储单元配置可以用1 F2的每个存储单元的平均面积要求来生成，其中F是最小结构尺寸。

8. 发明授权

US07838925B2 Integrated circuit including a vertical transistor and method 有权
标题翻译：集成电路包括垂直晶体管和方法
公开(公告)号：US07838925B2
公开(公告)日：2010-11-23
申请号：US12173524
申请日：2008-07-15
申请人： Wolfgang Roesner , Franz Hofmann
发明人： Wolfgang Roesner , Franz Hofmann
IPC分类号： H01L29/732
CPC分类号： H01L29/7827 , H01L21/2255 , H01L27/108 , H01L27/10802 , H01L27/10876 , H01L29/0878 , H01L29/0886 , H01L29/1083 , H01L29/1095 , H01L29/41766 , H01L29/42356 , H01L29/66734 , H01L29/7813
摘要： An integrated circuit including a vertical transistor and method of manufacturing. In one embodiment a vertical transistor is formed in a pillar of a semiconductor substrate. A buried conductive line is separated from the semiconductor substrate by a first insulating layer in a first portion and is electrically coupled to a buried source/drain region of the vertical transistor through a contact structure. A second insulating layer is arranged above and adjacent to the contact structure. At least one of the first and second insulating layers includes a dopant. A doped region is formed in the semiconductor substrate at an interface to the at least one insulating layer. The doped region has a dopant concentration higher than a substrate dopant concentration.
摘要翻译：一种包括垂直晶体管和制造方法的集成电路。在一个实施例中，垂直晶体管形成在半导体衬底的柱中。埋入导线通过第一部分中的第一绝缘层与半导体衬底分离，并通过接触结构电耦合到垂直晶体管的掩埋源/漏区。第二绝缘层布置在接触结构的上方并与之相邻。第一和第二绝缘层中的至少一个包括掺杂剂。掺杂区域形成在半导体衬底中与至少一个绝缘层的界面处。掺杂区域的掺杂浓度高于衬底掺杂剂浓度。

9. 发明授权

US07829892B2 Integrated circuit including a gate electrode 有权
标题翻译：集成电路包括栅电极
公开(公告)号：US07829892B2
公开(公告)日：2010-11-09
申请号：US11926653
申请日：2007-10-29
申请人： Richard Johannes Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Roesner , Till Schloesser , Michael Specht
发明人： Richard Johannes Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Roesner , Till Schloesser , Michael Specht
IPC分类号： H01L29/12
CPC分类号： H01L27/10823 , H01L27/10808 , H01L27/10826 , H01L27/10829 , H01L27/10891 , H01L29/7851
摘要： An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at least two opposite sides.
摘要翻译：公开了一种包括栅电极的集成电路。一个实施例提供一种晶体管，其包括第一源极/漏极电极和第二源极/漏极电极。在半导体衬底中的第一和第二源极/漏极之间布置有沟道。栅电极被布置在沟道层附近并且与沟道层电绝缘。半导体基板电极设置在后侧。栅极电极将沟道层包围至少两个相对的侧面。

10. 发明申请

US20100013005A1 INTEGRATED CIRCUIT INCLUDING A VERTICAL TRANSISTOR AND METHOD 有权
标题翻译：集成电路，包括垂直晶体管和方法
公开(公告)号：US20100013005A1
公开(公告)日：2010-01-21
申请号：US12173524
申请日：2008-07-15
申请人： Wolfgang Roesner , Franz Hofmann
发明人： Wolfgang Roesner , Franz Hofmann
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L21/2255 , H01L27/108 , H01L27/10802 , H01L27/10876 , H01L29/0878 , H01L29/0886 , H01L29/1083 , H01L29/1095 , H01L29/41766 , H01L29/42356 , H01L29/66734 , H01L29/7813
摘要： An integrated circuit including a vertical transistor and method of manufacturing. In one embodiment a vertical transistor is formed in a pillar of a semiconductor substrate. A buried conductive line is separated from the semiconductor substrate by a first insulating layer in a first portion and is electrically coupled to a buried source/drain region of the vertical transistor through a contact structure. A second insulating layer is arranged above and adjacent to the contact structure. At least one of the first and second insulating layers includes a dopant. A doped region is formed in the semiconductor substrate at an interface to the at least one insulating layer. The doped region has a dopant concentration higher than a substrate dopant concentration.
摘要翻译：一种包括垂直晶体管和制造方法的集成电路。在一个实施例中，垂直晶体管形成在半导体衬底的柱中。埋入导线通过第一部分中的第一绝缘层与半导体衬底分离，并通过接触结构电耦合到垂直晶体管的掩埋源/漏区。第二绝缘层布置在接触结构的上方并与之相邻。第一和第二绝缘层中的至少一个包括掺杂剂。掺杂区域形成在半导体衬底中与至少一个绝缘层的界面处。掺杂区域的掺杂浓度高于衬底掺杂剂浓度。

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