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1. 发明授权

US5912845A Method and circuit for substrate current induced hot e.sup.- injection (SCIHE) approach for V.sub.T convergence at low V.sub.CC voltage 失效
标题翻译：用于在低VCC电压下VT收敛的衬底电流感应热电子注入（SCIHE）方法和电路
公开(公告)号：US5912845A
公开(公告)日：1999-06-15
申请号：US926554
申请日：1997-09-10
申请人： Chia-Shing Chen , Mam-Tsung Wang , Wenpin Lu , Ming-Hung Chou , Ying-Che Lo , Ming-Shang Chen
发明人： Chia-Shing Chen , Mam-Tsung Wang , Wenpin Lu , Ming-Hung Chou , Ying-Che Lo , Ming-Shang Chen
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C16/107 , G11C16/3404 , G11C16/3409 , G11C16/3445
摘要： A method for soft programming memory cells and floating gate memory device. During soft programming, a gate voltage is supplied to the control gate, a drain voltage it supplied to the drain, a well voltage is supplied to the well, and an active current limiter is coupled to the source. A circuit for soft programming supplies a gate voltage to the control gate, couples a constant current source to the drain, supplies a well voltage to the well, and supplies a source voltage to the source. The gate voltage may be approximately 2 V, the drain voltage may be approximately 4 V, and the well voltage may be approximately -2 V. According to another embodiment of the invention, the gate voltage is approximately 2 V lower than the drain voltage, and the well voltage is approximately 4 V lower than the gate voltage.
摘要翻译：一种用于软编程存储单元和浮动栅极存储器件的方法。在软编程期间，向控制栅极提供栅极电压，将其提供给漏极的漏极电压，将阱电压提供给阱，并且有源限流器耦合到源极。用于软编程的电路向控制栅极提供栅极电压，将恒定电流源耦合到漏极，将阱电压提供给阱，并将源电压提供给源极。栅极电压可以为约2V，漏极电压可以为约4V，并且阱电压可以为约-2V。根据本发明的另一实施例，栅极电压比漏极电压低约2V，并且阱电压比栅极电压低约4V。

2. 发明授权

US6031766A Method and circuit for substrate current induced hot e-injection (SCIHE) approach for V.sub.T convergence at low V.sub.cc voltage 有权
标题翻译：用于在低Vcc电压下VT收敛的衬底电流感应热电子注入（SCIHE）方法和电路
公开(公告)号：US6031766A
公开(公告)日：2000-02-29
申请号：US289697
申请日：1999-04-09
申请人： Chia-Shing Chen , Mam-Tsung Wang , Wenpin Lu , Ming-Hung Chou , Ying-Che Lo , Ming-Shang Chen
发明人： Chia-Shing Chen , Mam-Tsung Wang , Wenpin Lu , Ming-Hung Chou , Ying-Che Lo , Ming-Shang Chen
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C16/107 , G11C16/3404 , G11C16/3409 , G11C16/3445
摘要： A method for soft programming memory cells and floating gate memory device. During soft programming, a gate voltage is supplied to the control gate, a drain voltage it supplied to the drain, a well voltage is supplied to the well, and an active current limiter is coupled to the source. A circuit for soft programming supplies a gate voltage to the control gate, couples a constant current source to the drain, supplies a well voltage to the well, and supplies a source voltage to the source. The gate voltage may be approximately 2 V, the drain voltage may be approximately 4 V, and the well voltage may be approximately -2 V. According to another embodiment of the invention, the gate voltage is approximately 2 V lower than the drain voltage, and the well voltage is approximately 4 V lower than the gate voltage.
摘要翻译：一种用于软编程存储单元和浮动栅极存储器件的方法。在软编程期间，向控制栅极提供栅极电压，将其提供给漏极的漏极电压，将阱电压提供给阱，并且有源限流器耦合到源极。用于软编程的电路向控制栅极提供栅极电压，将恒定电流源耦合到漏极，将阱电压提供给阱，并将源电压提供给源极。栅极电压可以为约2V，漏极电压可以为约4V，并且阱电压可以为约-2V。根据本发明的另一实施例，栅极电压比漏极电压低约2V，并且阱电压比栅极电压低约4V。

3. 发明授权

US5912844A Method for flash EEPROM data writing 失效
标题翻译：闪存EEPROM数据写入方法
公开(公告)号：US5912844A
公开(公告)日：1999-06-15
申请号：US015606
申请日：1998-01-28
申请人： Chia-Shing Chen , Mam-Tsung Wang
发明人： Chia-Shing Chen , Mam-Tsung Wang
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/3459 , G11C16/10
摘要： Method for writing data to a NOR-type flash memory array including loading page data to a bit-latch buffer, programming cells to low threshold voltage V.sub.t, and programming cells to high V.sub.t. Programming cells to high V.sub.t by either: Channel Hot Electron Injection (CHEI) or Source Side Injection (SSI). CHEI releases the band-to-band induced hot hole damage while SSI further reduces the sector size to be the same as page size for NOR-type flash EEPROM memory.
摘要翻译：将数据写入NOR型闪存阵列的方法，包括将页面数据加载到位锁存缓冲器，将单元编程为低阈值电压Vt，并将单元编程为高Vt。通过以下方式将单元编程为高Vt：通道热电子注入（CHEI）或源侧注射（SSI）。 CHEI释放频带到频带引起的热孔损坏，而SSI进一步将扇区大小与NOR型闪存EEPROM存储器的页面大小相同。

4. 发明授权

US5959892A Apparatus and method for programming virtual ground EPROM array cell without disturbing adjacent cells 失效
标题翻译：用于编程虚拟接地EPROM阵列单元而不干扰相邻单元的装置和方法
公开(公告)号：US5959892A
公开(公告)日：1999-09-28
申请号：US918796
申请日：1997-08-26
申请人： Chin-Hsi Lin , Shi-Charng Ai , Chien-Sing Lee , Ful-Long Ni , Mam-Tsung Wang , Chin-Yi Huang
发明人： Chin-Hsi Lin , Shi-Charng Ai , Chien-Sing Lee , Ful-Long Ni , Mam-Tsung Wang , Chin-Yi Huang
IPC分类号： G11C11/56 , G11C16/10 , G11C16/34 , G11C16/04
CPC分类号： G11C16/3481 , G11C11/5621 , G11C11/5628 , G11C16/10 , G11C16/34 , G11C16/3468 , G11C16/0491 , G11C16/08 , G11C16/30 , G11C8/14
摘要： The present invention provides a method and an apparatus for programming a selected call within a virtual ground EPROM array cell without disturbing adjacent array cells. The electrical disturbance of data stored in adjacent cells is limited in a number of ways: (1) a column connection circuit is provided for selectively coupling together adjacent pairs of even-odd or odd-even column lines so that source and drain terminals of adjacent memory cells are electrically coupled together, thereby preventing the data stored within the adjacent cells from being disturbed; (2) a current limiter circuit is provided for lowering a potential on a terminal of the selected cell at a controlled rate during programming so that voltages on terminals of the selected cell do not disturb data stored on adjacent memory cells; (3) the order in which programming signals are applied to terminals of the selected cell are controlled in such a way as to reduce the disturbance of data on adjacent cells; and (4) high wordline and data line voltages are applied to the selected cell in two steps, first to an intermediate voltage, and then to a high voltage. This reduces the disturbance to adjacent cells and improves programming.
摘要翻译：本发明提供一种用于在虚拟接地EPROM阵列单元内编程所选择的呼叫而不干扰相邻阵列单元的方法和装置。存储在相邻小区中的数据的电扰动以多种方式受到限制：（1）提供列连接电路，用于选择性地将相邻的偶奇数或奇数偶数列对耦合在一起，使得相邻存储单元电耦合在一起，从而防止存储在相邻单元内的数据被干扰; （2）提供限流器电路，用于在编程期间以受控的速率降低所选择的单元的端子上的电位，使得所选单元的端子上的电压不会干扰存储在相邻存储单元上的数据; （3）将编程信号施加到所选择的单元的端子的顺序以减少相邻单元数据的干扰的方式进行控制; 和（4）将高字线和数据线电压分两步施加到所选择的单元，首先施加到中间电压，然后再施加到高电压。这减少了对相邻电池的干扰，并改善了编程。

5. 发明授权

US06397377B1 Method of performing optical proximity corrections of a photo mask pattern by using a computer 有权
标题翻译：通过使用计算机执行光掩模图案的光学邻近校正的方法
公开(公告)号：US06397377B1
公开(公告)日：2002-05-28
申请号：US09414899
申请日：1999-10-08
申请人： Bing-Ying Wang , Chun-Yi Yang , Chun-Jung Lin , Jui-Chin Chang , Mam-Tsung Wang
发明人： Bing-Ying Wang , Chun-Yi Yang , Chun-Jung Lin , Jui-Chin Chang , Mam-Tsung Wang
IPC分类号： G06F1750
CPC分类号： G03F1/36
摘要： The present invention provides a method of performing optical proximity corrections of a photo mask pattern by using a computer. The photo mask pattern is formed on a photo mask which is used when performing photolithography for forming a predetermined original pattern by exposing a photo-resist layer in a predetermined area of a semiconductor wafer. The photo mask pattern is divided into a plurality of rectangular blocks. Each block can be bright or dark, and a least one side and two corners of the block are shared with another block. Each of shared corners is checked to find corners which may be affected by an optic proximity effect, and those corners are modified so as to prevent them from being affected by the optic proximity effect.
摘要翻译：本发明提供一种通过使用计算机执行光掩模图案的光学邻近校正的方法。光掩模图案形成在通过在半导体晶片的预定区域中曝光光刻胶层进行光刻以形成预定原始图案时使用的光掩模上。光掩模图案被分成多个矩形块。每个块可以是明亮的或暗的，并且该块的至少一个侧面和两个角与另一个块共享。检查每个共享拐角以找到可能受光学邻近效应影响的角部，并且修改这些拐角以防止它们受到光学邻近效应的影响。

6. 发明授权

US06269017B1 Multi level mask ROM with single current path 有权
标题翻译：具有单电流路径的多级掩模ROM
公开(公告)号：US06269017B1
公开(公告)日：2001-07-31
申请号：US09262374
申请日：1999-03-04
申请人： Tao-Cheng Lu , Chung Ju Chen , Mam-Tsung Wang
发明人： Tao-Cheng Lu , Chung Ju Chen , Mam-Tsung Wang
IPC分类号： G11C1710
CPC分类号： G11C11/5692 , G11C17/12 , H01L27/112
摘要： Mask ROMS with fixed code implantation and associated integrated circuits are described. An integrated circuit has a Mask ROM including: an array of memory cells including a first bank of memory cells and a second bank of memory cells, and the first bank of memory cells separated from the second bank of memory cell by a set of select lines, and the first bank of memory cells and the second bank of memory cells includes at least one fixed code implanted memory cell column. The use of fixed code implantation results in a single current path during the reading of a given memory cell and permits the size of the corresponding device to be reduced and have better topography. The Mask ROM provides additional advantages because the use of the same select transistors for two banks reduces the overhead of select transistors for a given size of array, the use of only one sense amplifier per block reduces the overhead of sense amplifiers for a given size of array, and the use of odd and even word line decoders divides the memory cell array into a number of banks.
摘要翻译：描述具有固定码植入和相关集成电路的掩模ROMS。集成电路具有掩模ROM，该掩模ROM包括：包括第一存储单元组和第二存储单元组的存储单元阵列，以及通过一组选择线与第二存储单元组分离的第一存储单元组并且所述第一存储单元组和所述第二存储单元组包括至少一个固定代码植入存储单元列。在给定存储单元的读取期间，使用固定代码注入导致单个电流路径，并允许相应的器件的尺寸减小并具有更好的形貌。掩模ROM提供了额外的优点，因为对于两个存储体使用相同的选择晶体管降低了给定尺寸阵列的选择晶体管的开销，每个块仅使用一个读出放大器减少了给定尺寸的读出放大器的开销阵列，并且奇数和偶数字线解码器的使用将存储单元阵列划分成多个存储体。

7. 发明授权

US6166943A Method of forming a binary code of a ROM 有权
标题翻译：形成ROM的二进制码的方法
公开(公告)号：US6166943A
公开(公告)日：2000-12-26
申请号：US421260
申请日：1999-10-20
申请人： Ping-Ying Wang , Chun-Yi Yang , Chun-Jung Lin , Jui-Chin Chang , Mam-Tsung Wang
发明人： Ping-Ying Wang , Chun-Yi Yang , Chun-Jung Lin , Jui-Chin Chang , Mam-Tsung Wang
IPC分类号： G11C17/10 , G11C17/00
CPC分类号： G11C17/10
摘要： The present invention provides a method of writing a set of binary codes into a ROM. The method is performed by forming a first photo mask and a second photo mask according to an original first code pattern, an original second code pattern, and a set of binary codes to be written into the ROM. Final first and second code patterns are formed by coupling the binary codes to be written with the original first and second code patterns by using a Boolean logical OR operation. The first and second photo masks are formed according to the final first and second code patterns. The first photolithographic process is performed using the first photo mask, and the first ion implantation process is performed; the second photolithographic process is performed using the second photo mask, and the second ion implantation process is performed. Thus the set of binary codes is written into the ROM completely and correctly.
摘要翻译：本发明提供了将一组二进制码写入到ROM中的方法。该方法通过根据原始第一代码图案，原始第二代码图案和要写入ROM的一组二进制代码形成第一光掩模和第二光掩模来执行。最终的第一和第二代码模式通过使用布尔逻辑“或”运算来耦合待写入的二进制代码与原始的第一和第二代码模式而形成。根据最终的第一和第二编码模式形成第一和第二光掩膜。使用第一光掩模执行第一光刻工艺，并且执行第一离子注入工艺; 使用第二光掩模进行第二光刻工序，进行第二离子注入工序。因此，二进制代码集完全正确地写入ROM中。

8. 发明授权

US06614687B2 Current source component with process tracking characteristics for compact programmed Vt distribution of flash EPROM 有权
标题翻译：具有过程跟踪特性的电流源组件用于闪存EPROM的紧凑编程Vt分布
公开(公告)号：US06614687B2
公开(公告)日：2003-09-02
申请号：US09848786
申请日：2001-05-03
申请人： Ming-Shang Chen , Wenpin Lu , Baw-Chyuan Lin , Mam-Tsung Wang
发明人： Ming-Shang Chen , Wenpin Lu , Baw-Chyuan Lin , Mam-Tsung Wang
IPC分类号： G11C1134
CPC分类号： G11C16/12 , G11C11/5628 , G11C2211/565
摘要： A new structure and method with a process tracking current source component to program a flash EPROM memory is proposed. By applying a current source which varies not only with the process variation but also with the source bias of the cell being programmed, a self-convergent and high-efficiency programming can be achieved. This process tracking current source component provides less current for cells with higher erased Vt and larger current for cells with lower erased Vt. A circuit for programming a floating gate transistor includes a current source component. The current source component couples in series between the floating gate transistor and an electrical sink during a programming interval. The current source component includes an electrical characteristic substantially matching the electrical characteristic of the floating gate transistor. An integrated circuit memory module on a semiconductor substrate is disclosed. The integrated circuit memory module includes: an array of floating gate memory cells, decoders, and a plurality of current source components. The array of floating gate memory cells is arranged in M rows and N columns. The decoders couple to the M rows and N columns of memory cells to provide for reading and programming floating gate memory cells within a selected one of the M rows of the memory array. The plurality of current source components each couple in series between an electrical sink and a corresponding one of the floating gate memory cells within the selected one of the M rows during a programming interval. Each of the plurality of current source components includes an electrical characteristic substantially matching the electrical characteristic of the corresponding one of the floating gate memory cells to be programmed.
摘要翻译：提出了一种具有过程跟踪电流源组件来编程闪存EPROM存储器的新结构和方法。通过应用电流源，其不仅随工艺变化而变化，而且随着被编程的电池的源偏置而变化，可以实现自收敛和高效率的编程。该过程跟踪电流源组件为具有较高擦除Vt的电池的电池提供更少的电流，并且具有较低擦除Vt的电池的电流较小。用于编程浮动栅晶体管的电路包括电流源组件。在编程间隔期间，电流源元件串联耦合在浮栅晶体管和电汇之间。电流源组件包括基本上与浮栅晶体管的电特性匹配的电特性。公开了半导体衬底上的集成电路存储器模块。集成电路存储器模块包括：浮动栅极存储器单元，解码器和多个电流源组件的阵列。浮栅存储单元的阵列排列成M行N列。解码器耦合到存储器单元的M行和N列，以提供在存储器阵列的M行中选定的一个中的读取和编程浮动栅极存储器单元。在编程间隔期间，多个电流源分量各自串联在电汇与所选择的M行之一内的浮动栅极存储单元中的对应的一个浮动栅极存储单元之间。多个电流源组件中的每一个包括基本上匹配要编程的浮动栅极存储单元中的相应一个的电特性的电特性。

9. 发明授权

US5895241A Method for fabricating a cell structure for mask ROM 失效
标题翻译：掩模ROM的单元结构的制造方法
公开(公告)号：US5895241A
公开(公告)日：1999-04-20
申请号：US825301
申请日：1997-03-28
申请人： Tao Cheng Lu , Mam-Tsung Wang
发明人： Tao Cheng Lu , Mam-Tsung Wang
IPC分类号： H01L21/8246
CPC分类号： H01L27/1124
摘要： A mask read-only-memory cell structure without ROM code implantation is presented. By using double polysilicon technology, ROM code cells which store data "0" can be replaced by cells with double polysilicon layers and an insulating layer between them. Normal cells with double polysilicon layers but without an insulating layer between them form normal cells store data "1". According to the invention, further scaling of mask ROM is possible and operating condition can be released because of high junction breakdown voltage. Furthermore, the double polysilicon technology makes redundancy circuit more easily to implement.
摘要翻译：提出了一种没有ROM代码植入的掩模只读存储单元结构。通过使用双重多晶硅技术，存储数据“0”的ROM代码单元可以由具有双多晶硅层的单元和它们之间的绝缘层代替。具有双多晶硅层但在它们之间没有绝缘层的正电池形成正常电池存储数据“1”。根据本发明，掩模ROM的进一步缩放是可能的，并且由于高的结击穿电压可以释放操作条件。此外，双晶体技术使得冗余电路更容易实现。

10. 发明授权

US5828113A Double density MROM array structure 失效
标题翻译：双重密度MROM阵列结构
公开(公告)号：US5828113A
公开(公告)日：1998-10-27
申请号：US825820
申请日：1997-03-28
申请人： Chung-Ju Chen , Mam-Tsung Wang
发明人： Chung-Ju Chen , Mam-Tsung Wang
IPC分类号： G11C17/12 , H01L21/8246 , H01L27/112 , H01L29/786
CPC分类号： H01L27/1128 , G11C17/12 , H01L27/112
摘要： A semiconductor mask-programmable read-only-memory array structure provides double density storage of data information by means of thin film memory cell transistors formed on both sides of a layer of thin film polysilicon. At a bottom surface of a layer of thin film polysilicon which has a bottom gate oxide grown thereon, a plurality of polysilicon bottom cell wordlines intersects a plurality of bitlines to form an array of bottom cell memory transistors. The bitlines are heavily-doped diffusion regions within the layer thin film polysilicon. Additionally, a top surface of the layer of thin film polysilicon has a top gate oxide grown thereon. Over this top gate oxide, a plurality of polysilicon top cell wordlines intersects the plurality of bitlines to form an array of top cell memory transistors, thereby producing a NOR-type read-only-memory array structure with double the storage density of conventional, prior art structures.
摘要翻译：半导体掩模可编程只读存储器阵列结构通过形成在薄膜多晶硅层两侧的薄膜存储单元晶体管提供数据信息的双重密度存储。在其上生长有底栅氧化物的薄膜多晶硅层的底表面上，多个多晶硅底单元字线与多个位线相交以形成底单元存储晶体管的阵列。位线是层薄膜多晶硅内的重掺杂扩散区。此外，薄膜多晶硅层的顶表面上生长有顶栅氧化物。在该顶栅极氧化物上，多个多晶硅顶部单元字线与多个位线相交以形成顶部单元存储晶体管的阵列，从而产生具有常规先前存储密度的两倍的NOR型只读存储器阵列结构艺术结构。

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