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1. 发明申请

WO2017196379A1 NON-LINEARITY CANCELLATION IN A DUAL-PATH ADC 审中-公开
标题翻译：双路ADC中的非线性消除
公开(公告)号：WO2017196379A1
公开(公告)日：2017-11-16
申请号：PCT/US2016/038277
申请日：2016-06-19
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD. , ZANBAGHI, Ramin , MORTAZAVI, Yousof , BRENNAN, Aaron , MELANSON, John, L.
发明人： ZANBAGHI, Ramin , MORTAZAVI, Yousof , BRENNAN, Aaron , MELANSON, John, L.
IPC分类号： H03M1/10 , H03M1/18 , H03M1/60
CPC分类号： H03M1/0602 , G10L19/00 , H03M1/1004 , H03M1/1038 , H03M1/1042 , H03M1/188 , H03M1/60
摘要： The overall performance of a dual-path ADC system may be improved by using a VCO-based ADC for small-amplitude signals and employing non-linear cancelation to remove nonlinearities in signals output by the VCO-based ADC. In particular, VCO-based dual-path ADC systems of this disclosure may be configured to receive a first digital signal from a first ADC and a second digital signal from a second ADC, wherein the second digital signal is more non-linear than the first digital signal. The dual-path systems may also be configured to determine one or more non-linear coefficients of the second digital signal based, at least in part, on processing of the first and second digital signals. The dual-path systems may be further configured to modify the second digital signal based, at least in part, on the determined one or more non-linear coefficients to generate a more linear second digital signal.
摘要翻译：双路ADC系统的整体性能可以通过使用基于VCO的ADC用于小幅度信号并采用非线性消除来消除基于VCO的输出信号中的非线性来改善 ADC。具体而言，本公开的基于VCO的双路径ADC系统可以被配置为接收来自第一ADC的第一数字信号和来自第二ADC的第二数字信号，其中第二数字信号比第一数字信号更为非线性数字信号。双路径系统还可以被配置为至少部分地基于第一和第二数字信号的处理来确定第二数字信号的一个或多个非线性系数。双路径系统可以进一步被配置为至少部分地基于所确定的一个或多个非线性系数来修改第二数字信号以生成更线性的第二数字信号。

2. 发明申请

WO2017030839A1 DUAL PROCESSING PATHS FOR DIFFERENTIAL MODE AND COMMON MODE SIGNALS FOR AN ADAPTABLE ANALOG-TO-DIGITAL CONVERTER (ADC) TOPOLOGY 审中-公开
标题翻译：用于适应模数转换器（ADC）拓扑学的差分模式和共模信号的双处理模式
公开(公告)号：WO2017030839A1
公开(公告)日：2017-02-23
申请号：PCT/US2016/046194
申请日：2016-08-09
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD. , ZANBAGHI, Ramin , MORTAZAVI, Yousof , BRENNAN, Aaron , MELANSON, John, L.
发明人： ZANBAGHI, Ramin , MORTAZAVI, Yousof , BRENNAN, Aaron , MELANSON, John, L.
IPC分类号： H03M1/12 , H03M3/00 , H04R19/04
CPC分类号： H03M1/14 , G06F3/16 , G11C27/024 , H03F3/005 , H03F3/45475 , H03F3/45959 , H03F2203/45421 , H03F2203/45512 , H03F2203/45544 , H03F2203/45551 , H03M1/124 , H03M1/1295 , H03M3/458 , H03M3/494 , H03M3/496 , H04R3/00 , H04R19/04 , H04R29/004 , H04R2499/11
摘要： One method of processing microphone input in an ADC to determine microphone configuration is to process the microphone input signals in two processing paths, in which one processing path processes a difference between differential input signals and another processing path processes an average value of the differential input signals. The outputs of these processing paths may be combined to generate a digital signal representative of the analog signal from the microphone. The digital signal contains a digital version of the audio in the environment around the microphone, but may also be used to detect microphone topology and configure aspects of the processing paths to match the detected microphone topology. An apparatus for an ADC may implement the two processing paths as two delta-sigma modulator loops.
摘要翻译：在ADC中处理麦克风输入以确定麦克风配置的一种方法是在两个处理路径中处理麦克风输入信号，其中一个处理路径处理差分输入信号之间的差异和另一个处理路径处理差分输入信号的平均值。这些处理路径的输出可以被组合以产生表示来自麦克风的模拟信号的数字信号。数字信号包含麦克风周围环境中的音频的数字版本，但也可用于检测麦克风拓扑并配置处理路径的各个方面以匹配检测到的麦克风拓扑结构。用于ADC的装置可以将两个处理路径实现为两个Δ-Σ调制器环路。

3. 发明申请

WO2017011145A1 VOLTAGE-CONTROLLED OSCILLATOR (VCO) AS FIRST STAGE IN AN ANALOG-TO-DIGITAL CONVERTER (ADC) IN COMBINATION WITH A DIGITAL FILTER FOR SECOND OR HIGHER-ORDER NOISE SHAPING 审中-公开
标题翻译：电压控制振荡器（VCO）作为模数转换器（ADC）中的第一级与数字滤波器组合用于第二或更高阶噪声形状
公开(公告)号：WO2017011145A1
公开(公告)日：2017-01-19
申请号：PCT/US2016/038271
申请日：2016-06-19
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD. , ZANBAGHI, Ramin , BRENNAN, Aaron , MELANSON, John, L.
发明人： ZANBAGHI, Ramin , BRENNAN, Aaron , MELANSON, John, L.
IPC分类号： H03M3/02
CPC分类号： H03M3/438 , H03M1/60
摘要： A delta-sigma modulation analog-to-digital converter (ADC) may be constructed by combining a VCO used for a first order filter with a digital loop filter used for a second or higher order of the ADC. One such ADC would include an analog input node configured to receive an analog signal; a voltage-controlled oscillator (VCO) comprising a first input configured to receive the analog signal, wherein the voltage-controlled oscillator is configured to implement a first order noise-shaping function; a digital loop filter comprising a second input configured to receive an output of the voltage-controlled oscillator (VCO); and a digital output node configured to output a digital signal based on an output of the digital loop filter. The digital loop filter may be configured to implement at least a first order noise-shaping function, but may also implement higher order noise-shaping functions.
摘要翻译：可以通过将用于一阶滤波器的VCO与用于第二或更高阶的ADC的数字环路滤波器组合来构造Δ-Σ调制模数转换器（ADC）。一个这样的ADC将包括被配置为接收模拟信号的模拟输入节点; 压控振荡器（VCO），包括被配置为接收所述模拟信号的第一输入，其中所述压控振荡器被配置为实现一阶噪声整形功能; 数字环路滤波器，包括被配置为接收压控振荡器（VCO）的输出的第二输入; 以及数字输出节点，被配置为基于数字环路滤波器的输出来输出数字信号。数字环路滤波器可以被配置为实现至少一阶噪声整形功能，但也可以实现更高阶的噪声整形功能。

4. 发明申请

WO2017030994A1 PHASE SHORTING SWITCH 审中-公开
标题翻译：相位短路开关
公开(公告)号：WO2017030994A1
公开(公告)日：2017-02-23
申请号：PCT/US2016/046881
申请日：2016-08-12
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD. , ZANBAGHI, Ramin , BRENNAN, Aaron , ALLEN, Daniel, J. , MELANSON, John, L.
发明人： ZANBAGHI, Ramin , BRENNAN, Aaron , ALLEN, Daniel, J. , MELANSON, John, L.
IPC分类号： H03M1/12 , H04R19/04 , H03F3/45
CPC分类号： H03M1/14 , G06F17/11 , G11C27/024 , H03F3/005 , H03F3/45475 , H03F3/45959 , H03F2203/45421 , H03F2203/45512 , H03F2203/45544 , H03F2203/45551 , H03M1/124 , H03M1/1295 , H03M3/458 , H03M3/496 , H04R3/00 , H04R19/04 , H04R29/004 , H04R2420/05 , H04R2499/11
摘要： An analog-to-digital converter (ADC) may include capability to sense and/or compensate for undesired effects when receiving input from a microphone. For example, a sense node may be provided between differential inputs, and that sense node separated from the differential inputs by two or more switches. The sense node may allow for a measurement of an average voltage of the differential inputs. The average voltage may be obtained activating the switches to sample the sampling capacitors coupled to the differential inputs. That average voltage may be used as common mode (CM) data. A controller may receive the CM data, along with differential mode (DM) data, and use the CM and DM data to determine undesired effects, such as DC or AC mismatch at the microphone interface. The controller may then generate a signal for applying compensation to the differential inputs to reduce or eliminate the undesired effects.
摘要翻译：模数转换器（ADC）可以包括当从麦克风接收输入时感测和/或补偿不期望的效果的能力。例如，可以在差分输入之间提供感测节点，并且感测节点可以由两个或更多个开关与差分输入分离。感测节点可以允许差分输入的平均电压的测量。可以获得平均电压来激活开关以采样耦合到差分输入的采样电容器。该平均电压可以用作共模（CM）数据。控制器可以与差分模式（DM）数据一起接收CM数据，并使用CM和DM数据来确定不期望的效果，例如麦克风接口处的DC或AC失配。然后，控制器可以生成用于向差分输入施加补偿的信号，以减少或消除不期望的影响。

5. 发明申请

WO2018102370A1 NOISE REDUCTION IN VOLTAGE REFERENCE SIGNAL 审中-公开
公开(公告)号：WO2018102370A1
公开(公告)日：2018-06-07
申请号：PCT/US2017/063639
申请日：2017-11-29
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD. , ZANBAGHI, Ramin , DAS, Tejasvi , MELANSON, John, L. , THOMSEN, Axel
发明人： ZANBAGHI, Ramin , DAS, Tejasvi , MELANSON, John, L. , THOMSEN, Axel
IPC分类号： H03M1/08 , H03M1/12
摘要： A variable resistor may be coupled between a reference voltage source and components of an integrated circuit to reduce issues relating to thermal noise from a reference voltage signal generated by the reference voltage source. The variable resistor may be set to a low level during a first time period and a high level during a second time period, in which the time periods correspond to a sampling period of a switched-capacitor circuit. The low resistance time period may allow quick settling of an input reference voltage signal, whereas the high resistance time period may reduce a bandwidth of noise on a sampling capacitor coupled to the reference voltage signal. The variable resistor and switched-capacitor network may be used in an analog-to-digital converter (ADC), such as in audio circuits.

6. 发明申请

WO2022165345A1 COMMON MODE OUTPUT VOLTAGE BIASING IN CLASS-D AUDIO AMPLIFIERS HAVING SELECTABLE DIFFERENTIAL OR DUAL SINGLE-ENDED OPERATION AND CLASS-D ZERO-CROSSING MANAGEMENT 审中-公开
公开(公告)号：WO2022165345A1
公开(公告)日：2022-08-04
申请号：PCT/US2022/014577
申请日：2022-01-31
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD. , PETERSON, Cory J. , MELANSON, John L. , PRAKASH, Chandra , ZANBAGHI, Ramin , KIMBALL, Eric
发明人： PETERSON, Cory J. , MELANSON, John L. , PRAKASH, Chandra , ZANBAGHI, Ramin , KIMBALL, Eric
IPC分类号： H03F3/217 , H03F1/02 , H03F3/20 , H03F3/21
摘要： A class-D amplifier provides low-distortion operation near one of the output power supply rails. The class-D amplifier has a first driver circuit, a second driver circuit and a control circuit. In some embodiments, the control circuit selects between a single-ended operating state and a differential operating state. The control logic may selectively determine the input of the second driver circuit in conformity with a current operating state of the class-D amplifier circuit so that a first differential modulator circuit operates both drivers in a differential operating state. In other embodiments, the control circuit selects between actively operating a selected one of the driver circuits or both, while setting an unselected driver circuit to turn either a high-side switch or a low-side switch of the unselected one of the first driver circuit or the second driver circuit fully on for at least some cycles of the one or more modulators.

7. 发明申请

WO2019036579A1 MULTI-PATH ANALOG SYSTEM WITH MULTI-MODE HIGH-PASS FILTER 审中-公开
公开(公告)号：WO2019036579A1
公开(公告)日：2019-02-21
申请号：PCT/US2018/046863
申请日：2018-08-17
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR, LTD. , ZANBAGHI, Ramin
发明人： ZANBAGHI, Ramin , ALLEN, Daniel J. , MELANSON, John L. , SATOSKAR, Aniruddha , GODBOLE, Akshay , DEY, Siladitya
IPC分类号： H03M1/08 , H03M1/18
摘要： A system may comprise a high-pass filter having an input for receiving an input signal, an output for generating an output signal, a capacitor coupled between the input and the output, a switched-capacitor resistor coupled between the output and a reference voltage, and control circuitry configured to control the reference voltage to cancel current leakage into a circuit coupled to the output. The input, the output, the capacitor, and the switched-capacitor resistor may be arranged to generate the output signal as a high-pass filtered version of the input signal and the high-pass filter may be configured to operate in a plurality of modes comprising at least a high-impedance mode and a low-impedance mode in which the resistance of the switched-capacitor resistor is significantly smaller than the resistance when in the high-impedance mode. A system may include a plurality of processing paths having a first path configured to generate a first digital signal based on an analog input signal and a second path configured to generate a second digital signal based on the analog input signal, the second path having a high-pass filter for filtering the analog input signal prior to the analog input signal being processed by the remainder of the second path, and the high-pass filter having a corner frequency. Control circuitry may be configured to determine frequency-dependent weighted proportions of the first and second digital signals to be combined into an output digital signal based on a characteristic of the analog input signal. Frequency-dependent weighted proportions may be such that the digital output signal includes spectral content of the first digital signal below the corner frequency to account for spectral content of the second digital signal below the corner frequency being filtered. A system may include an input for receiving an input signal, an output for generating an output signal, a capacitor coupled between the input and the output, a variable resistor coupled to the output and having a plurality of modes including a first mode in which the variable resistor has a first resistance and a second mode in which the variable resistor has a second resistance, and control circuitry configured to determine a difference between the input signal and the output signal and switch between modes of the plurality of modes when the difference is less than a predetermined threshold.

8. 发明申请

WO2022159236A1 DUAL-CHANNEL CLASS-D AUDIO AMPLIFIER HAVING QUANTIZER-COMBINED ORTHOGONAL MODULATION 审中-公开
公开(公告)号：WO2022159236A1
公开(公告)日：2022-07-28
申请号：PCT/US2021/065294
申请日：2021-12-28
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD. , PETERSON, Cory J. , PRAKASH, Chandra , ZANBAGHI, Ramin , KIMBALL, Eric
发明人： PETERSON, Cory J. , PRAKASH, Chandra , ZANBAGHI, Ramin , KIMBALL, Eric
IPC分类号： H03F3/217 , H03F3/68
摘要： Class-D amplifiers and modulators therefor provide control of the DC operating point of the outputs of the amplifiers. The modulators generate a sum and difference signal using combiners and introduce the sum signal to a reference input of the quantizer, while the quantization input of the quantizer receives the difference signal. A difference mode loop filter circuit may filter the difference signal and a common mode loop filter may filter the sum signal. Outputs of the quantizer operate a pair of switching circuits to provide either a differential output with the sum signal set to a constant voltage and the difference signal provided by the signal to be reproduced, or a pair of single-ended outputs with the individual input signals used to generate the sum and difference signal, and selection of a differential or dual single-ended operating mode may be performed by a control circuit that reconfigures the combiners.

9. 发明申请

WO2020081220A1 CHOPPED TRIANGULAR WAVE PWM QUANTIZER AND PWM MODULATOR HAVING QUANTIZER WITH CONTROLLABLE ANALOG GAIN AND CALIBRATABLE FOR MULTI-NON-IDEAL GAIN-AFFECTING CHARACTERISTICS 审中-公开
公开(公告)号：WO2020081220A1
公开(公告)日：2020-04-23
申请号：PCT/US2019/053735
申请日：2019-09-30
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD. , ZANBAGHI, Ramin , MELANSON, John , LEE, Kyehyung , PARSI, Anuradha
发明人： ZANBAGHI, Ramin , MELANSON, John , LEE, Kyehyung , PARSI, Anuradha
IPC分类号： H03K4/50 , H03F3/217
摘要： An apparatus in a PWM modulator includes a triangular wave generator that generates a triangular wave and a comparator that is responsive to a signal input to generate a signal output. An output of the PWM modulator is responsive to the comparator signal output. A polarity inversion circuit, coupled between the triangular wave generator and the comparator, is configured in one of the following ways: to provide the triangular wave to the comparator when the triangular wave has a first slope polarity and to provide a polarity-inverted version of the triangular wave to the comparator when the triangular wave has a second slope polarity opposite the first slope polarity; and to provide the signal input to the comparator when the triangular wave has the first slope polarity and to provide a polarity-inverted version of the signal input to the comparator when the triangular wave has the second slope polarity.

10. 发明申请

WO2016170413A8 ANALOG-TO-DIGITAL CONVERTER (ADC) DYNAMIC RANGE ENHANCEMENT FOR VOICE-ACTIVATED SYSTEMS 审中-公开
公开(公告)号：WO2016170413A8
公开(公告)日：2016-10-27
申请号：PCT/IB2016/000496
申请日：2016-04-04
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.
发明人： MORTAZAVI, Yousof , MELANSON, John, L. , ZANBAGHI, Ramin , BRENNAN, Aaron
IPC分类号： H03M1/18 , G10L25/78
摘要： The dynamic range and power efficiency of a voice-activated system may be improved by dynamically adjusting the configuration of the voice-activated system's input path. In one embodiment, a first portion of audio may be received through an input path of the voice- activated system having a first configuration. A characteristic of the first portion of audio may be determined and the input path may be adjusted to a second configuration based on the determined characteristic. A second portion of audio may then be received through the input path having the second configuration, and speech analysis may be performed on the second portion of audio.

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