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1. 发明授权

US07332414B2 Chemical die singulation technique 有权
标题翻译：化学模切技术
公开(公告)号：US07332414B2
公开(公告)日：2008-02-19
申请号：US11159553
申请日：2005-06-22
申请人： Brian W. Condie , David J. Dougherty , Mahesh K. Shah
发明人： Brian W. Condie , David J. Dougherty , Mahesh K. Shah
IPC分类号： H01L21/00
CPC分类号： H01L21/78
摘要： A method is provided for manufacturing a semiconductor device from a substrate (200) having an active surface (204) and a non-active surface (206). The method comprises depositing a backing material (104) onto the non-active surface of the substrate (206) in a pattern (500), the pattern (500) having at least a first die section (210), a second die section (212) adjacent the first die section (210), and a strip (216) connecting the first die section (210) and the second die section (212), removing material from portions of the non-active surface of the substrate (206) on which the backing material (104) is not deposited to thereby partially separate the substrate (200) into a first die (236) and a second die (238) connected to one another by the strip (254) of the deposited backing material, and breaking the strip connector (254) to separate the first die (236) from the second die (238).
摘要翻译：提供了一种从具有有源表面（204）和非有效表面（206）的衬底（200）制造半导体器件的方法。该方法包括以图案（500）将背衬材料（104）沉积到基底（206）的非活性表面上，图案（500）具有至少第一模具部分（210），第二模具部分 212），以及连接第一模具部分（210）和第二模具部分（212）的条带（216），从衬底（206）的非活性表面的部分去除材料，其上不沉积背衬材料（104），从而通过沉积的背衬材料的带（254）将衬底（200）部分地分离成第一模具（236）和第二模具（238），所述第一模具（238）彼此连接，以及断开带状连接器（254）以将第一管芯（236）与第二管芯（238）分离。

2. 发明授权

US07435625B2 Semiconductor device with reduced package cross-talk and loss 有权
标题翻译：半导体器件具有减少的封装串扰和损耗
公开(公告)号：US07435625B2
公开(公告)日：2008-10-14
申请号：US11257802
申请日：2005-10-24
申请人： Brian W. Condie , Mali Mahalingam , Mahesh K. Shah
发明人： Brian W. Condie , Mali Mahalingam , Mahesh K. Shah
IPC分类号： H01L21/00
CPC分类号： H01L23/3135 , H01L23/295 , H01L23/4334 , H01L24/48 , H01L2224/05553 , H01L2224/48247 , H01L2224/97 , H01L2924/00014 , H01L2924/01021 , H01L2924/09701 , H01L2924/10161 , H01L2924/14 , H01L2924/181 , H01L2924/3025 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Structure and method are provided for plastic encapsulated semiconductor devices having reduced package cross-talk and loss. Semiconductor die are first coated with a buffer region having a lower dielectric constant ε and/or lower loss tangent δ than the plastic encapsulation. The encapsulation surrounds the buffer region providing a solid structure. The lower ε buffer region reduces the stray capacitance and therefore the cross-talk between electrodes on or coupled to the die. The lower δ buffer region reduces the parasitic loss in the encapsulation. Low ε and/or δ buffer regions can be achieved using low density organic and/or inorganic materials. Another way is to disperse hollow microspheres or other fillers in the buffer region. An optional sealing layer formed between the buffer region and the encapsulation can mitigate any buffer layer porosity. The buffer region desirably has ε less than about 3.0 and/or δ less than about 0.005.
摘要翻译：提供了具有降低的封装串扰和损耗的塑料封装的半导体器件的结构和方法。半导体管芯首先被涂覆有比塑料封装具有更低的介电常数ε和/或更低的损耗角正切delta的缓冲区。封装围绕提供固体结构的缓冲区。较低的ε缓冲区域减小了杂散电容，并因此降低了电极之间或耦合到裸片上的串扰。较低的Δ缓冲区减少了封装中的寄生损耗。可以使用低密度有机和/或无机材料实现低ε和/或δ缓冲区。另一种方法是将中空微球或其它填料分散在缓冲区中。形成在缓冲区和封装之间的可选密封层可以缓解任何缓冲层的孔隙度。缓冲区域希望具有小于约3.0的ε和/或小于约0.005的Δ。

3. 发明申请

US20090001614A1 SEMICONDUCTOR DEVICE WITH A BUFFER REGION WITH TIGHTLY-PACKED FILLER PARTICLES 失效
标题翻译：带缓冲区的半导体器件，带有紧密包装的填料颗粒
公开(公告)号：US20090001614A1
公开(公告)日：2009-01-01
申请号：US12204500
申请日：2008-09-04
申请人： Brian W. Condie , Mali Mahalingam , Mahesh K. Shah
发明人： Brian W. Condie , Mali Mahalingam , Mahesh K. Shah
IPC分类号： H01L23/495 , H01L23/29
CPC分类号： H01L23/3135 , H01L23/295 , H01L23/4334 , H01L24/48 , H01L2224/05553 , H01L2224/48247 , H01L2224/97 , H01L2924/00014 , H01L2924/01021 , H01L2924/09701 , H01L2924/10161 , H01L2924/14 , H01L2924/181 , H01L2924/3025 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An embodiment of a semiconductor device includes a supporting member, a semiconductor die mounted on a portion of the supporting member, a buffer region, and a plastic encapsulation. The buffer region covers a portion of the die, and includes a resin and filler particles packed within the resin. The filler particles have a mix of filler sizes and are tightly packed within the resin. The buffer region has a first dielectric constant and a first loss tangent. The plastic encapsulation encloses at least part of the supporting member and the die. The plastic encapsulation includes a plastic material of a second dielectric constant and a second loss tangent, where the second dielectric constant is larger than the first dielectric constant and the second loss tangent is larger than the first loss tangent.
摘要翻译：半导体器件的实施例包括支撑构件，安装在支撑构件的一部分上的半导体管芯，缓冲区域和塑料封装。缓冲区域覆盖模具的一部分，并且包括填充在树脂内的树脂和填料颗粒。填料颗粒具有填料尺寸的混合物并且紧密地包装在树脂内。缓冲区具有第一介电常数和第一损耗角正切。塑料封装包围支撑构件和模具的至少一部分。塑料封装包括第二介电常数和第二损耗角正切的塑料材料，其中第二介电常数大于第一介电常数，第二损耗角正切大于第一损耗角正切。

4. 发明授权

US07432133B2 Plastic packaged device with die interface layer 有权
标题翻译：带芯片接口层的塑料封装装置
公开(公告)号：US07432133B2
公开(公告)日：2008-10-07
申请号：US11257822
申请日：2005-10-24
申请人： Brian W. Condie , Mahesh K. Shah
发明人： Brian W. Condie , Mahesh K. Shah
IPC分类号： H01L21/48
CPC分类号： H01L23/3192 , H01L23/3164 , H01L23/3171 , H01L23/4334 , H01L24/97 , H01L2224/48091 , H01L2924/01004 , H01L2924/01005 , H01L2924/01021 , H01L2924/01033 , H01L2924/01057 , H01L2924/01074 , H01L2924/01082 , H01L2924/09701 , H01L2924/14 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： Structure and method are provided for plastic encapsulated semiconductor devices having a buffer layer of low dielectric constant and/or low loss tangent material separating the die surface from the plastic encapsulation. Semiconductor wafers with substantially completed SC die are coated with the buffer layer. The buffer layer is patterned to expose the die bonding pads but leave the buffer layer over some or all of the other die metallization. The die are then separated, mounted on a lead-frame or other support, wire bonded or otherwise coupled to external leads, and encapsulated. The plastic encapsulation surrounds the die and the buffer layer, providing a solid structure. The buffer layer reduces the parasitic capacitance, cross-talk and loss between metallization regions on the die. An optional sealing layer may also be provided at the wafer stage between the buffer layer and the plastic encapsulation to mitigate any buffer layer porosity.
摘要翻译：提供了具有低介电常数和/或低损耗正切材料的缓冲层的塑料封装的半导体器件的结构和方法，其将管芯表面与塑料封装分开。具有基本上完成的SC管芯的半导体晶片被缓冲层涂覆。图案化缓冲层以露出芯片焊盘，但是将缓冲层留在其它芯片金属化部分或全部上。然后将管芯分离，安装在引线框架或其他支撑件上，引线键合或以其他方式耦合到外部引线，并封装。塑料封装围绕裸片和缓冲层，提供坚实的结构。缓冲层减少了裸片上的金属化区域之间的寄生电容，串扰和损耗。也可以在缓冲层和塑料封装之间的晶片台处设置可选的密封层，以减轻任何缓冲层孔隙率。

5. 发明授权

US07701074B2 Semiconductor device with a buffer region with tightly-packed filler particles 失效
标题翻译：半导体器件具有紧密填充填料颗粒的缓冲区
公开(公告)号：US07701074B2
公开(公告)日：2010-04-20
申请号：US12204500
申请日：2008-09-04
申请人： Brian W. Condie , L. M. Mahalingam , Mahesh K. Shah
发明人： Brian W. Condie , L. M. Mahalingam , Mahesh K. Shah
IPC分类号： H01L23/29
CPC分类号： H01L23/3135 , H01L23/295 , H01L23/4334 , H01L24/48 , H01L2224/05553 , H01L2224/48247 , H01L2224/97 , H01L2924/00014 , H01L2924/01021 , H01L2924/09701 , H01L2924/10161 , H01L2924/14 , H01L2924/181 , H01L2924/3025 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An embodiment of a semiconductor device includes a supporting member, a semiconductor die mounted on a portion of the supporting member, a buffer region, and a plastic encapsulation. The buffer region covers a portion of the die, and includes a resin and filler particles packed within the resin. The filler particles have a mix of filler sizes and are tightly packed within the resin. The buffer region has a first dielectric constant and a first loss tangent. The plastic encapsulation encloses at least part of the supporting member and the die. The plastic encapsulation includes a plastic material of a second dielectric constant and a second loss tangent, where the second dielectric constant is larger than the first dielectric constant and the second loss tangent is larger than the first loss tangent.
摘要翻译：半导体器件的实施例包括支撑构件，安装在支撑构件的一部分上的半导体管芯，缓冲区域和塑料封装。缓冲区域覆盖模具的一部分，并且包括填充在树脂内的树脂和填料颗粒。填料颗粒具有填料尺寸的混合物并且紧密地包装在树脂内。缓冲区具有第一介电常数和第一损耗角正切。塑料封装包围支撑构件和模具的至少一部分。塑料封装包括第二介电常数和第二损耗角正切的塑料材料，其中第二介电常数大于第一介电常数，第二损耗角正切大于第一损耗角正切。

6. 发明授权

US07683480B2 Methods and apparatus for a reduced inductance wirebond array 有权
标题翻译：减小电感引线阵列的方法和装置
公开(公告)号：US07683480B2
公开(公告)日：2010-03-23
申请号：US11393582
申请日：2006-03-29
申请人： Mario M. Bokatius , Peter H. Aaen , Brian W. Condie
发明人： Mario M. Bokatius , Peter H. Aaen , Brian W. Condie
IPC分类号： H01L23/24
CPC分类号： H01L23/552 , H01L23/642 , H01L23/66 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L2223/6611 , H01L2224/05554 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48011 , H01L2224/48091 , H01L2224/48137 , H01L2224/48195 , H01L2224/48472 , H01L2224/49175 , H01L2224/49176 , H01L2224/49433 , H01L2224/85205 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/10329 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/00014 , H01L2924/00
摘要： A wirebond array (100) comprising a plurality of signal wires 110 and a plurality of ground wires (120) interdigitated with and substantially parallel to the set of signal wires (110). In one embodiment, each of the plurality of signal wires (110) and ground wires (120) is attached to a first semiconductor device (102) (e.g., a microwave power device). In another, each of the plurality of signal wires (110) is further attached to a package lead (104). In one embodiment, each of the plurality of ground wires (120) is further attached to a ground connection region (106) substantially coplanar with the package lead (104). Alternatively, each of the plurality of signal wires (110) is further attached to a second semiconductor device, wherein each of the plurality of ground wires (120) is further attached to the second semiconductor device.
摘要翻译：一种引线键盘阵列（100），包括多个信号线110和与该组信号线（110）交叉并基本上平行的多个接地线（120）。在一个实施例中，多个信号线（110）和接地线（120）中的每一个连接到第一半导体器件（102）（例如，微波功率器件）。在另一个中，多个信号线（110）中的每一个进一步连接到封装引线（104）。在一个实施例中，多个接地线（120）中的每一个进一步连接到基本上与封装引线（104）共面的接地连接区域（106）。或者，多个信号线（110）中的每一个还被附接到第二半导体器件，其中多个接地线（120）中的每一个进一步附接到第二半导体器件。

7. 发明授权

US07042103B2 Low stress semiconductor die attach 失效
标题翻译：低应力半导体芯片附着
公开(公告)号：US07042103B2
公开(公告)日：2006-05-09
申请号：US10334042
申请日：2002-12-30
申请人： Brian W. Condie , David J. Dougherty
发明人： Brian W. Condie , David J. Dougherty
IPC分类号： H01L23/52
CPC分类号： H01L24/83 , H01L23/562 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/29299 , H01L2224/32014 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/73265 , H01L2224/8319 , H01L2224/83801 , H01L2224/83805 , H01L2224/8385 , H01L2924/00013 , H01L2924/00014 , H01L2924/00015 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01041 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/0133 , H01L2924/0134 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10329 , H01L2924/15747 , H01L2924/181 , H01L2924/3511 , H01L2924/00 , H01L2924/01014 , H01L2924/01028 , H01L2924/01083 , H01L2924/3512 , H01L2224/29099 , H01L2224/29199 , H01L2224/05599 , H01L2224/85399 , H01L2224/45099 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device (121) is provided which comprises a substrate and a die (123) having a first surface which is attached to the substrate by way of a die attach material. At least a portion (127) of the perimeter of the die is resistant to wetting by the die attach material, either through treatment with a dewetting agent or by selective removal of the backside metallization. It is found that this construction allows the surface area of the die to be increased without increasing the incidence of cracking and chipping along the sawn edges of the die.
摘要翻译：提供一种半导体器件（121），其包括基板和具有通过管芯附着材料附接到基板的第一表面的管芯（123）。通过用去湿剂处理或通过选择性去除背面金属化，模具的周边的至少一部分（127）抵抗通过管芯附接材料的润湿。发现这种结构允许模具的表面积增加，而不增加沿着模具的锯刃的开裂和切屑的发生。

8. 发明授权

US07429790B2 Semiconductor structure and method of manufacture 有权
标题翻译：半导体结构及制造方法
公开(公告)号：US07429790B2
公开(公告)日：2008-09-30
申请号：US11257783
申请日：2005-10-24
申请人： Brian W. Condie , Lakshminarayan Viswanathan , Richard W. Wetz
发明人： Brian W. Condie , Lakshminarayan Viswanathan , Richard W. Wetz
IPC分类号： H01L23/10
CPC分类号： H01L23/13 , H01L23/10 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/45111 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48464 , H01L2224/49 , H01L2224/73265 , H01L2224/92 , H01L2224/92247 , H01L2924/01007 , H01L2924/01014 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/10253 , H01L2924/10329 , H01L2924/12044 , H01L2924/15153 , H01L2924/1517 , H01L2924/16195 , H01L2924/181 , H01L2924/18301 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/01025 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor structure (100) includes a substrate (110) having a first surface (111) with a mold lock feature (101). The semiconductor structure also includes a semiconductor chip (120) located over the first surface of the substrate. The semiconductor structure further includes an electrical isolator structure (340) located over the first surface of the substrate. The electrical isolator structure includes an electrical lead (341, 342) and an electrically insulative element (343) molded to the electrical lead. An optional portion (444) of the electrical isolator structure is located in the mold lock feature. The semiconductor structure additionally includes an adhesive element (450) located between and coupling the electrical isolator structure and the first surface of the substrate.
摘要翻译：半导体结构（100）包括具有模具锁定特征（101）的第一表面（111）的基板（110）。半导体结构还包括位于衬底的第一表面上方的半导体芯片（120）。半导体结构还包括位于衬底的第一表面上方的电隔离器结构（340）。电隔离器结构包括电引线（341,342）和模制到电引线上的电绝缘元件（343）。电隔离器结构的可选部分（444）位于模具锁定特征中。半导体结构还包括位于电隔离器结构和衬底的第一表面之间的耦合的粘合元件（450）。

9. 发明授权

US07446411B2 Semiconductor structure and method of assembly 有权
标题翻译：半导体结构及组装方法
公开(公告)号：US07446411B2
公开(公告)日：2008-11-04
申请号：US11257784
申请日：2005-10-24
申请人： Brian W. Condie , Lakshminarayan Viswanathan , Richard W. Wetz
发明人： Brian W. Condie , Lakshminarayan Viswanathan , Richard W. Wetz
IPC分类号： H01L23/10
CPC分类号： H01L23/10 , H01L23/047 , H01L23/053 , H01L23/057 , H01L23/66 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/50 , H01L24/83 , H01L24/85 , H01L25/072 , H01L25/50 , H01L2223/6644 , H01L2224/16 , H01L2224/29111 , H01L2224/29116 , H01L2224/29144 , H01L2224/2929 , H01L2224/29299 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48464 , H01L2224/49 , H01L2224/73265 , H01L2224/83801 , H01L2224/83851 , H01L2224/85 , H01L2224/92247 , H01L2924/00011 , H01L2924/00013 , H01L2924/01006 , H01L2924/01007 , H01L2924/01014 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/09701 , H01L2924/10253 , H01L2924/10329 , H01L2924/157 , H01L2924/16195 , H01L2924/16315 , H01L2924/181 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/00014 , H01L2924/01025 , H01L2924/01026 , H01L2924/3512 , H01L2924/00 , H01L2924/0665 , H01L2224/29099 , H01L2224/29199 , H01L2224/83205
摘要： A semiconductor structure (100, 900) includes a substrate (110) having a surface (111) and also includes one or more semiconductor chips (120) located over the substrate surface. The semiconductor structure further includes an electrical isolator structure (340) located over the substrate surface, where the electrical isolator structure includes one or more electrical leads (341, 342) and an organic-based element (343) molded to the electrical leads. The semiconductor structure also includes a solder element (350) coupling together the electrical isolator structure and the substrate surface.
摘要翻译：半导体结构（100,900）包括具有表面（111）的衬底（110），并且还包括位于衬底表面上方的一个或多个半导体芯片（120）。半导体结构还包括位于衬底表面上的电隔离器结构（340），其中电隔离器结构包括一个或多个电引线（341,342）和模制到电引线的有机元件（343）。半导体结构还包括将电隔离器结构和衬底表面耦合在一起的焊料元件（350）。

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