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1. 发明授权

US08664118B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08664118B2
公开(公告)日：2014-03-04
申请号：US13539907
申请日：2012-07-02
申请人： Akihiro Ishizuka , Kazuya Hanaoka , Shinya Sasagawa , Sho Nagamatsu
发明人： Akihiro Ishizuka , Kazuya Hanaoka , Shinya Sasagawa , Sho Nagamatsu
IPC分类号： H01L21/302
CPC分类号： H01L21/02422 , H01L21/02488 , H01L21/02554 , H01L21/02565 , H01L21/02658 , H01L21/02661 , H01L21/3105 , H01L29/66969 , H01L29/78636 , H01L29/7869
摘要： An object is to provide a semiconductor device having excellent characteristics, in which a channel layer includes an oxide semiconductor with high crystallinity. In addition, a semiconductor device including a base film with improved planarity is provided. CMP treatment is performed on the base film of the transistor and plasma treatment is performed thereon after the CMP treatment, whereby the base film can have a center line average roughness Ra75 of less than 0.1 nm. The oxide semiconductor layer with high crystallinity is formed over the base film having planarity, which is obtained by the combination of the plasma treatment and the CMP treatment, thereby improving the characteristics of the semiconductor device.
摘要翻译：目的在于提供具有优异特性的半导体器件，其中沟道层包括具有高结晶度的氧化物半导体。此外，提供了包括具有改善的平面度的基膜的半导体器件。在晶体管的基膜上进行CMP处理，在CMP处理之后进行等离子体处理，由此基膜的中心线平均粗糙度Ra75可以小于0.1nm。在通过等离子体处理和CMP处理的组合获得的具有平坦度的基膜上形成具有高结晶度的氧化物半导体层，从而提高半导体器件的特性。

2. 发明授权

US09431545B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09431545B2
公开(公告)日：2016-08-30
申请号：US13604962
申请日：2012-09-06
申请人： Toshihiko Saito , Atsuo Isobe , Kazuya Hanaoka , Junichi Koezuka , Shinya Sasagawa , Motomu Kurata , Akihiro Ishizuka
发明人： Toshihiko Saito , Atsuo Isobe , Kazuya Hanaoka , Junichi Koezuka , Shinya Sasagawa , Motomu Kurata , Akihiro Ishizuka
IPC分类号： H01L29/786 , H01L21/28 , H01L27/12
CPC分类号： H01L29/7869 , H01L27/1225
摘要： A miniaturized transistor having high electric characteristics is provided with high yield. In a semiconductor device including the transistor, high performance, high reliability, and high productivity are achieved. In a semiconductor device including a transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, source and drain electrode layers are provided in contact with the oxide semiconductor film and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive film and an interlayer insulating film are stacked to cover the oxide semiconductor film, the sidewall insulating layers, and the gate electrode layer, and the interlayer insulating film and the conductive film over the gate electrode layer are removed by a chemical mechanical polishing method, so that the source and drain electrode layers are formed.
摘要翻译：提供具有高电特性的小型化晶体管，其产率高。在包括晶体管的半导体器件中，实现了高性能，高可靠性和高生产率。在包括晶体管的半导体器件中，依次堆叠其中设置有侧壁绝缘层的侧表面上的氧化物半导体膜，栅极绝缘膜和栅极电极层的晶体管，源极和漏极电极层被设置为与氧化物半导体膜和侧壁绝缘层。在制造半导体器件的过程中，层叠导电膜和层间绝缘膜以覆盖氧化物半导体膜，侧壁绝缘层和栅极电极层，以及栅极上的层间绝缘膜和导电膜通过化学机械抛光方法去除层，从而形成源极和漏极电极层。

3. 发明授权

US08841675B2 Minute transistor 有权
标题翻译：分钟晶体管
公开(公告)号：US08841675B2
公开(公告)日：2014-09-23
申请号：US13609931
申请日：2012-09-11
申请人： Toshihiko Saito , Atsuo Isobe , Kazuya Hanaoka , Sho Nagamatsu
发明人： Toshihiko Saito , Atsuo Isobe , Kazuya Hanaoka , Sho Nagamatsu
IPC分类号： H01L29/10 , H01L29/76 , H01L27/108 , H01L29/04 , H01L27/12 , H01L29/786 , H01L29/78
CPC分类号： H01L29/66969 , H01L21/02565 , H01L21/44 , H01L21/463 , H01L21/465 , H01L27/1225 , H01L27/14632 , H01L27/14687 , H01L29/04 , H01L29/78 , H01L29/7869
摘要： A minute transistor and the method of manufacturing the minute transistor. A source electrode layer and a drain electrode layer are each formed in a corresponding opening formed in an insulating layer covering a semiconductor layer. The opening of the source electrode layer and the opening of the drain electrode layer are formed separately in two distinct steps. The source electrode layer and the drain electrode layer are formed by depositing a conductive layer over the insulating layer and in the openings, and subsequently removing the part located over the insulating layer by polishing. This manufacturing method allows for the source electrode later and the drain electrode layer to be formed close to each other and close to a channel forming region of the semiconductor layer. Such a structure leads to a transistor having high electrical characteristics and a high manufacturing yield even in the case of a minute structure.
摘要翻译：一分钟晶体管和微晶体管的制造方法。源极电极层和漏极电极层各自形成在形成在覆盖半导体层的绝缘层中的对应的开口中。源电极层的开口和漏电极层的开口分开形成两个不同的步骤。源极电极层和漏电极层通过在绝缘层上和开口中沉积导电层而形成，然后通过抛光去除位于绝缘层之上的部分。该制造方法允许稍后的源极电极和漏极电极层彼此靠近并且靠近半导体层的沟道形成区域。这种结构导致即使在微小结构的情况下也具有高电特性和高制造成品率的晶体管。

4. 发明授权

US08530973B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08530973B2
公开(公告)日：2013-09-10
申请号：US13547393
申请日：2012-07-12
申请人： Kazuya Hanaoka , Miki Suzuki
发明人： Kazuya Hanaoka , Miki Suzuki
IPC分类号： H01L29/786
CPC分类号： H01L21/76823 , H01L21/76825 , H01L25/0657 , H01L27/124 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： It is an object to form a conductive region in an insulating film without forming contact holes in the insulating film. A method is provided, in which an insulating film is formed over a first electrode over a substrate, a first region having many defects is formed at a first depth in the insulating film by adding first ions into the insulating film at a first accelerating voltage; a second region having many defects is formed at a second depth which is different from the first depth in the insulating film by adding second ions into the insulating film at a second accelerating voltage, a conductive material containing a metal element is formed over the first and second regions; and a conductive region which electrically connects the first electrode and the conductive material is formed in the insulating film by diffusing the metal element into the first and second regions.
摘要翻译：其目的是在绝缘膜中形成导电区域，而不在绝缘膜中形成接触孔。提供了一种方法，其中在衬底上方的第一电极上形成绝缘膜，通过以第一加速电压将绝缘膜中加入第一离子，在绝缘膜的第一深度处形成具有许多缺陷的第一区域; 通过在第二加速电压下将第二离子加入到绝缘膜中，在第二深度上形成具有许多缺陷的第二区域，该第二深度与绝缘膜中的第一深度不同，在第一深度上形成包含金属元素的导电材料，第二区; 并且通过将金属元素扩散到第一和第二区域中，在绝缘膜中形成电连接第一电极和导电材料的导电区域。

5. 发明授权

US08486772B2 Method of manufacturing SOI substrate 有权
标题翻译：制造SOI衬底的方法
公开(公告)号：US08486772B2
公开(公告)日：2013-07-16
申请号：US13454114
申请日：2012-04-24
申请人： Kazuya Hanaoka , Hideki Tsuya , Masaharu Nagai
发明人： Kazuya Hanaoka , Hideki Tsuya , Masaharu Nagai
IPC分类号： H01L21/00 , H01L21/46 , H01L21/20 , H01L21/461
CPC分类号： H01L21/76254
摘要： The method of one embodiment of the present invention includes: a first step of irradiating a bond substrate with ions to form an embrittlement region in the bond substrate; a second step of bonding the bond substrate to a base substrate with an insulating layer therebetween; a third step of splitting the bond substrate at the embrittlement region to form a semiconductor layer over the base substrate with the insulating layer therebetween; and a fourth step of subjecting the bond substrate split at the embrittlement region to a first heat treatment in an argon atmosphere and then a second heat treatment in an atmosphere of a mixture of oxygen and nitrogen to form a reprocessed bond substrate. The reprocessed bond substrate is used again as a bond substrate in the first step.
摘要翻译：本发明的一个实施方案的方法包括：第一步骤，用离子照射键合衬底，以在接合衬底中形成脆化区; 将所述接合衬底粘合到其上具有绝缘层的基底衬底的第二步骤; 在所述脆化区域分割所述键合衬底以在所述基底衬底上形成半导体层并在其间具有绝缘层的第三步骤; 以及第四步骤，将在脆化区域分裂的键合衬底在氩气氛中进行第一次热处理，然后在氧和氮的混合气氛中进行第二次热处理，以形成再加工的接合衬底。在第一步中再次使用再加工的键合衬底作为键合衬底。

6. 发明授权

US08415228B2 Manufacturing method of SOI substrate and semiconductor device 有权
标题翻译： SOI衬底和半导体器件的制造方法
公开(公告)号：US08415228B2
公开(公告)日：2013-04-09
申请号：US12555825
申请日：2009-09-09
申请人： Kazuya Hanaoka , Takashi Shingu , Taichi Endo
发明人： Kazuya Hanaoka , Takashi Shingu , Taichi Endo
IPC分类号： H01L21/30
CPC分类号： H01L21/76254
摘要： To provide a manufacturing method of a semiconductor device in which, even when the semiconductor device is formed over an SOI substrate which uses a glass substrate, an insulating film and a semiconductor film over the glass substrate are not peeled by stress applied by a conductive film in formation of the conductive film for forming a gate electrode. A semiconductor device is manufactured by the steps of forming a first insulating film over a bond substrate, forming an embrittlement layer by adding ions from a surface of the bond substrate, bonding the bond substrate to a glass substrate with the first insulating film interposed therebetween, separating the bond substrate along the embrittlement layer to form a semiconductor film over the glass substrate with the first insulating film interposed therebetween, removing a peripheral region of the first insulating film and the semiconductor film to expose part of the glass substrate, forming a gate insulating film over and in contact with the semiconductor film and the glass substrate, and forming a stacked conductive film over and in contact with the gate insulating film, in which the stacked conductive film includes a conductive film having a tensile stress and a conductive film having a compressive stress.
摘要翻译：为了提供一种半导体器件的制造方法，其中即使半导体器件形成在使用玻璃衬底的SOI衬底上，绝缘膜和玻璃衬底上的半导体膜也不会被导电膜施加的应力剥离形成用于形成栅电极的导电膜。通过以下步骤制造半导体器件：通过在接合衬底上形成第一绝缘膜，通过从接合衬底的表面添加离子形成脆化层，将接合衬底与第一绝缘膜接合在玻璃衬底上，沿着所述脆化层分离所述接合衬底，以在所述玻璃衬底上形成半导体膜，并且在所述玻璃衬底之间插入所述第一绝缘膜，除去所述第一绝缘膜和所述半导体膜的周边区域，以暴露所述玻璃衬底的一部分，形成栅极绝缘并且与半导体膜和玻璃基板接触并且形成与栅极绝缘膜接触的层叠导电膜，其中层叠导电膜包括具有拉伸应力的导电膜和具有拉伸应力的导电膜压应力。

7. 发明授权

US08698697B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08698697B2
公开(公告)日：2014-04-15
申请号：US12135373
申请日：2008-06-09
申请人： Teruyuki Fujii , Kazuya Hanaoka
发明人： Teruyuki Fujii , Kazuya Hanaoka
IPC分类号： H01Q1/36 , G08B13/14 , G06K19/077
CPC分类号： H01Q1/364 , H01Q1/2225 , H01Q1/38 , H01Q9/27
摘要： In a semiconductor device in which a copper plating layer is used for a conductor of an antenna and in which an integrated circuit and the antenna are formed over the same substrate, an object is to prevent an adverse effect on electrical characteristics of a circuit element due to diffusion of copper, as well as to provide a copper plating layer with favorable adhesiveness. Another object is to prevent a defect in the semiconductor device that stems from poor connection between the antenna and the integrated circuit, in the semiconductor device in which the integrated circuit and the antenna are formed over the same substrate. In the semiconductor device, a copper plating layer is used for the antenna, an alloy of Ag, Pd, and Cu is used for a seed layer thereof, and TiN or Ti is used for a barrier layer.
摘要翻译：在其中使用镀铜层用于天线的导体并且集成电路和天线形成在同一衬底上的半导体器件中，目的是防止对电路元件的电特性的不利影响铜的扩散，以及提供具有良好粘合性的镀铜层。另一个目的是在集成电路和天线形成在同一衬底上的半导体器件中，防止由于天线和集成电路之间的不良连接导致的半导体器件中的缺陷。在半导体装置中，使用铜电镀层作为天线，使用Ag，Pd，Cu的合金作为种子层，使用TiN或Ti作为阻挡层。

8. 发明授权

US08288245B2 Reprocessing method of semiconductor substrate, manufacturing method of reprocessed semiconductor substrate, and manufacturing method of SOI substrate 有权
标题翻译：半导体衬底的再加工方法，再加工半导体衬底的制造方法以及SOI衬底的制造方法
公开(公告)号：US08288245B2
公开(公告)日：2012-10-16
申请号：US12894860
申请日：2010-09-30
申请人： Hideto Ohnuma , Kazuya Hanaoka
发明人： Hideto Ohnuma , Kazuya Hanaoka
IPC分类号： H01L21/30
CPC分类号： H01L21/02032 , H01L21/02024 , H01L21/30604 , H01L21/30608 , H01L21/324 , H01L21/3247 , H01L21/76254 , H01L21/84
摘要： An object of an embodiment of the disclosed invention is to provide a method suitable for reprocessing a semiconductor substrate which is reused to manufacture an SOI substrate. A semiconductor substrate is reprocessed in the following manner: etching treatment is performed on a semiconductor substrate in which a step portion including a damaged semiconductor region and an insulating layer exists in a peripheral portion, whereby the insulating layer is removed; etching treatment is performed on the semiconductor substrate with the use of a mixed solution including a substance that oxidizes a semiconductor material included in the semiconductor substrate, a substance that dissolves the oxidized semiconductor material, and a substance that controls oxidation speed of the semiconductor material and dissolution speed of the oxidized semiconductor material, whereby the damaged semiconductor region is selectively removed with a non-damaged semiconductor region left; and heat treatment under an atmosphere including hydrogen is performed.
摘要翻译：所公开的发明的一个实施例的目的是提供一种适于重新处理半导体衬底的方法，该半导体衬底被重新用于制造SOI衬底。以下列方式对半导体衬底进行再处理：在周边部分存在包括损坏的半导体区域和绝缘层的阶梯部分的半导体衬底上进行蚀刻处理，从而去除绝缘层; 使用包含氧化半导体衬底中所含的半导体材料的物质，溶解氧化半导体材料的物质和控制半导体材料的氧化速度的物质的混合溶液在半导体衬底上进行蚀刻处理，以及氧化的半导体材料的溶解速度，由此损坏的半导体区域被选择性地去除，其中未损坏的半导体区域留下; 并在包括氢气在内的气氛下进行热处理。

9. 发明申请

US20100270868A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100270868A1
公开(公告)日：2010-10-28
申请号：US12830195
申请日：2010-07-02
申请人： Kazuya Hanaoka , Hideto Ohnuma , Teruyuki Fujii
发明人： Kazuya Hanaoka , Hideto Ohnuma , Teruyuki Fujii
IPC分类号： H02J17/00 , H01L27/14
CPC分类号： H01Q1/2208 , H01Q9/0407 , H01Q23/00
摘要： An object of the present invention is to prevent electrical characteristics of circuit elements from being adversely affected by copper diffusion in a semiconductor device having an integrated circuit and an antenna formed over the same substrate, which uses copper plating for the antenna. Another object is to prevent a defect of a semiconductor device due to poor connection between an antenna and an integrated circuit in a semiconductor device having the integrated circuit and the antenna formed over the same substrate. In a semiconductor device having an integrated circuit 100 and an antenna 101 formed over one substrate 102, when a copper plating layer 108 is used for a conductor of the antenna 101, it is possible to prevent copper diffusion to circuit elements and decrease an adverse effect on electrical characteristics of circuit elements due to the copper diffusion because a base layer 107 of the antenna 101 uses a nitride film of a predetermined metal. Moreover, by the use of nickel nitride as a metal nitride for the base layer of the antenna, poor connection between the antenna and the integrated circuit can be decreased.
摘要翻译：本发明的目的是为了防止电路元件的电特性在具有集成电路的半导体器件和形成在同一衬底上的天线的铜扩散的不利影响，该天线使用用于天线的铜电镀。另一个目的是防止由于在具有集成电路的半导体器件中的天线和集成电路之间的连接不良而导致半导体器件的缺陷，并且天线形成在同一衬底上。在具有形成在一个基板102上的集成电路100和天线101的半导体器件中，当将铜镀层108用于天线101的导体时，可以防止铜扩散到电路元件并降低不利影响由于铜扩散而导致的电路元件的电特性，因为天线101的基极层107使用预定金属的氮化物膜。此外，通过使用氮化镍作为天线的基底层的金属氮化物，可以降低天线与集成电路之间的不良连接。

10. 发明授权

US09123529B2 Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate 有权
标题翻译：半导体基板的再加工方法，再加工半导体基板的制造方法以及SOI基板的制造方法
公开(公告)号：US09123529B2
公开(公告)日：2015-09-01
申请号：US13523011
申请日：2012-06-14
申请人： Kazuya Hanaoka , Shunsuke Kimura
发明人： Kazuya Hanaoka , Shunsuke Kimura
IPC分类号： H01L21/00 , H01L21/02 , H01L21/306 , H01L21/3105 , H01L21/311 , H01L21/762
CPC分类号： H01L21/02032 , H01L21/02238 , H01L21/02255 , H01L21/30604 , H01L21/3105 , H01L21/31111 , H01L21/76254
摘要： A method suitable to reprocess a semiconductor substrate is provided. A semiconductor substrate in which a projection including a damaged semiconductor region and an insulating layer is provided in a peripheral portion of the semiconductor substrate is subjected to etching treatment for removing the insulating layer and to etching treatment for removing the damaged semiconductor region selectively with a non-damaged semiconductor region left using a mixed solution including nitric acid, a substance dissolving a semiconductor material included in the semiconductor substrate and oxidized by the nitric acid, a substance controlling a speed of oxidation of the semiconductor material and a speed of dissolution of the oxidized semiconductor material, and nitrous acid, in which the concentration of the nitrous acid is higher than or equal to 10 mg/l and lower than or equal to 1000 mg/l. Through these steps, the semiconductor substrate is reprocessed.
摘要翻译：提供了适用于半导体衬底再加工的方法。对半导体衬底的周边部分设置有包含损坏的半导体区域和绝缘层的突起的半导体衬底进行用于去除绝缘层的蚀刻处理和用于非绝缘层选择性地去除损坏的半导体区域的蚀刻处理使用包含硝酸（溶解包含在半导体衬底中并由硝酸氧化的半导体材料的物质）的混合溶液留下的损坏的半导体区域，控制半导体材料的氧化速度的物质和氧化的半导体材料和亚硝酸，其中亚硝酸的浓度高于或等于10mg / l且小于或等于1000mg / l。通过这些步骤，再次处理半导体衬底。

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