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1. 发明申请

WO2017064454A1 AN APPARATUS AND METHOD FOR PROCESSING A RECEIVED INPUT SIGNAL CONTAINING A SEQUENCE OF DATA BLOCKS 审中-公开
标题翻译：用于处理包含数据块序列的接收到的输入信号的装置和方法
公开(公告)号：WO2017064454A1
公开(公告)日：2017-04-20
申请号：PCT/GB2016/052814
申请日：2016-09-12
申请人： ARM LIMITED
发明人： WHATMOUGH, Paul Nicholas , DAS, Shidhartha
IPC分类号： H04L25/06 , H04L25/03 , H04L25/49
CPC分类号： H04L25/069 , H04L25/03318 , H04L25/4902
摘要： An apparatus and method are provided for processing a received input signal comprising a sequence of data blocks. Counter circuitry within the apparatus is arranged to receive a digital representation of the input signal, and for each data block generates a count value indicative of occurrences of a property of the digital representation (for example a rising edge or a falling edge) during an associated data block transmission period. Quantization circuitry then maps each count value to a soft decision value from amongst a predetermined set of soft decision values, where the number of soft decision values in the predetermined set exceeds a number of possible data values of the data block. The output circuitry then generates a digital output signal in dependence on the soft decision values. Such an apparatus has been found to provide a low power technique for a receiver, whilst still enabling the improved sensitivity benefits of using soft decisions to be achieved, and allows the apparatus to be constructed using all digital components.
摘要翻译：提供了一种用于处理包括数据块序列的接收到的输入信号的装置和方法。设备内的计数器电路被设置为接收输入信号的数字表示，并且对于每个数据块，在相关联的过程中产生指示出现数字表示的特性（例如上升沿或下降沿）的计数值数据块传输周期。量化电路然后将每个计数值映射到预定的一组软判决值中的软判定值，其中该预定集合中的软判定值的数量超过数据块的可能数据值的数量。输出电路然后根据软判决值产生数字输出信号。已经发现这种装置为接收机提供低功率技术，同时仍然能够实现使用软判决的改进的灵敏度益处，并且允许使用所有数字组件构建装置。

2. 发明公开

EP3785263A1 METHOD, SYSTEM AND DEVICE FOR INTEGRATION OF VOLATILE AND NON-VOLATILE MEMORY BITCELLS 审中-实审
公开(公告)号：EP3785263A1
公开(公告)日：2021-03-03
申请号：EP19734452.6
申请日：2019-03-22
申请人： ARM Limited
发明人： BHARGAVA, Mudit , DAS, Shidhartha , LATTIMORE, George McNeil , CLINE, Brian Tracy
IPC分类号： G11C11/00 , G11C14/00 , G11C13/00 , G11C7/10 , G11C8/14 , G11C5/02 , G11C5/06 , G11C11/419 , G11C8/08 , G11C7/20

3. 发明公开

EP4139819A1 MODERATOR SYSTEM FOR A SECURITY ANALYTICS FRAMEWORK 审中-实审
公开(公告)号：EP4139819A1
公开(公告)日：2023-03-01
申请号：EP21728961.0
申请日：2021-04-16
申请人： ARM Limited
发明人： YANAMADALA, Subbayya Chowdary , DUBEUF, Jeremy Patrick , VINEYARD, Carl Wayne , BOETTCHER, Matthias Lothar , VINCENT, Hugo John Martin , DAS, Shidhartha
IPC分类号： G06F21/55 , G06N3/02 , G06N20/00

4. 发明公开

EP4139818A1 ANALYTICS PROCESSING CIRCUITRY FOR MITIGATING ATTACKS AGAINST COMPUTING SYSTEMS 审中-实审
公开(公告)号：EP4139818A1
公开(公告)日：2023-03-01
申请号：EP21721588.8
申请日：2021-04-14
申请人： ARM Limited
发明人： YANAMADALA, Subbayya Chowdary , DUBEUF, Jeremy Patrick , VINEYARD, Carl Wayne , BOETTCHER, Matthias Lothar , VINCENT, Hugo John Martin , DAS, Shidhartha
IPC分类号： G06F21/55 , G06F21/56 , G06F21/76

5. 发明申请

WO2021074558A1 ADAPTIVE CODING FOR WIRELESS COMMUNICATION 审中-公开
公开(公告)号：WO2021074558A1
公开(公告)日：2021-04-22
申请号：PCT/GB2020/050713
申请日：2020-03-18
申请人： ARM LIMITED , ECS PARTNERS LIMITED
发明人： GAMAGE, Sahan Sajeewa Hiniduma Udugama , FLETCHER, Benjamin James , DAS, Shidhartha
IPC分类号： H04L1/00 , H04L25/49
摘要： A method and apparatus for transferring data maps the data to a modulation code using an encoder circuit having a configuration. A binary symbol of the data is mapped to a modulation code having a plurality of modulation digits and a modulation signal is generated based on the modulation code. A transmitter drive signal is modulated based on the modulation signal. A configuration of the encoder circuit is set based on a determined performance level. The transmitter drive signal may be used to produce an electromagnetic field by generating a positive, negative or zero electrical current in an induction coil of a first semiconductor die. A current induced by the electromagnetic field in an induction coil of a second semiconductor die is demodulated to recover the data whereby the data is transferred from the first semiconductor die to the second semiconductor die.

6. 发明申请

WO2016174384A1 TRANSITION DETECTION CIRCUITRY AND METHOD OF DETECTING A TRANSITION OF A SIGNAL OCCURRING WITHIN A TIMING WINDOW 审中-公开
标题翻译：过渡检测电路及检测在时序窗口内发生信号转换的方法
公开(公告)号：WO2016174384A1
公开(公告)日：2016-11-03
申请号：PCT/GB2016/050561
申请日：2016-03-03
申请人： ARM LIMITED
发明人： DAS, Shidhartha , BULL, David Michael
IPC分类号： H03K5/1534 , H03K3/037
CPC分类号： H03K5/1534 , H03K3/037 , H03K3/0375
摘要： A transition detection circuit (20) and method of operation of such a circuit are provided, the transition detection circuit (20) having pulse generation circuitry (25) to receive an input signal (10) and to generate a pulse signal in response to a transition in the input signal, and pulse detection circuitry (30) to assert an error signal on detection of the pulse signal generated by the pulse generation circuitry. The pulse generation circuitry has pulse control circuitry (35) to control a property of the pulse signal dependent on a timing window indication signal (40). In particular, when the pulse signal is generated at least partly whilst the timing window indication signal is set, the pulse control circuitry (35) controls the property of the pulse signal such that generated pulse signal is detected by the pulse detection circuitry (20). In contrast, when the pulse signal is entirely generated whilst the timing window indication signal (40) is cleared, the pulse control circuitry (35) controls the property of the pulse signal such that the generated pulse signal is undetected by the pulse detection circuitry (20). This gives rise to significant area and energy consumption savings, whilst still allowing reliable detection of timing errors.
摘要翻译：提供了一种转换检测电路（20）和这种电路的操作方法，转换检测电路（20）具有接收输入信号（10）的脉冲发生电路（25），并产生响应于输入信号中的转换和脉冲检测电路（30），用于在由脉冲发生电路产生的脉冲信号的检测上断言误差信号。脉冲发生电路具有根据定时窗口指示信号（40）控制脉冲信号的特性的脉冲控制电路（35）。特别地，当在定时窗口指示信号被设定时至少部分产生脉冲信号时，脉冲控制电路（35）控制脉冲信号的特性，使脉冲检测电路（20）检测所产生的脉冲信号，。相反，当脉冲信号在定时窗口指示信号（40）被清除时完全产生时，脉冲控制电路（35）控制脉冲信号的特性，使得产生的脉冲信号不被脉冲检测电路检测（ 20）。这导致显着的面积和能量消耗节省，同时仍然允许可靠地检测定时误差。

7. 发明申请

WO2015170072A1 CLOCK FREQUENCY REDUCTION FOR AN ELECTRONIC DEVICE 审中-公开
标题翻译：电子设备的时钟频率降低
公开(公告)号：WO2015170072A1
公开(公告)日：2015-11-12
申请号：PCT/GB2015/050736
申请日：2015-03-13
申请人： ARM LIMITED
发明人： WHATMOUGH, Paul Nicholas , BULL, David Michael , DAS, Shidhartha
IPC分类号： G06F1/08
CPC分类号： G06F1/324 , G06F1/08
摘要： An electronic device (20) has a clock path (24) for propagating a clock signal and a clock propagating element (26) on the clock path. An analogue element (30) coupled to the clock path (24) varies, in dependence on an analogue level of a first signal (32), a switching delay for the clock propagating element (26) to trigger a transition of the clock signal. The first signal is a digitally sampled signal. This provides a mechanism for providing a fast reduction in clock frequency even if the first signal is a metastable signal, which is useful for avoiding errors causes by voltage drops.
摘要翻译：电子设备（20）具有用于在时钟路径上传播时钟信号和时钟传播元件（26）的时钟路径（24）。耦合到时钟路径（24）的模拟元件（30）根据第一信号（32）的模拟电平而变化用于时钟传播元件（26）触发时钟信号转换的切换延迟。第一个信号是数字采样信号。这提供了即使第一信号是亚稳态信号来提供时钟频率的快速降低的机制，其可用于避免由电压降引起的错误。

8. 发明申请

WO2022200763A1 METHOD AND APPARATUS FOR COMMUNICATION VIA INDUCTIVE COUPLING 审中-公开
公开(公告)号：WO2022200763A1
公开(公告)日：2022-09-29
申请号：PCT/GB2022/050532
申请日：2022-02-28
申请人： ARM LIMITED , ECS PARTNERS LIMITED
发明人： FLETCHER, Benjamin James , MYERS, James Edward , DAS, Shidhartha , GAMAGE, Sahan Sajeewa Hiniduma Udugama
IPC分类号： H04B5/00
摘要： The present disclosure provides a method and apparatus for communicating between dice of an inductively-coupled 3D integrated circuit (3D-IC). A transmit resonant circuit at a transmit die is inductively coupled to a first receive resonant circuit at a first receive die, and to a second receive resonant circuit at a second receive die. The resonant circuit at the targeted receive die is tuned to the frequency of resonance of the transmit resonant circuit, while the resonant circuit at the untargeted receive die is detuned, resulting in lower power consumption for a given bit error rate at the targeted die.

9. 发明申请

WO2021094714A1 SYSTEM-IN-PACKAGE ARCHITECTURE WITH WIRELESS BUS INTERCONNECT 审中-公开
公开(公告)号：WO2021094714A1
公开(公告)日：2021-05-20
申请号：PCT/GB2020/052806
申请日：2020-11-05
申请人： ARM LIMITED , ECS PARTNERS LIMITED
发明人： FLETCHER, Benjamin James , MYERS, James Edward , DAS, Shidhartha , MAK, Terrence Sui Tung
IPC分类号： H01L23/522 , G06F13/00 , H01L25/065 , H01Q23/00 , H04B5/00 , H04B5/02 , H01L25/07
摘要： A chip-carrier package includes a data processing system having one or more slave dies, a master die and a system bus. Each slave die includes a slave device and a slave-side wireless bus interface (WBI) coupled to the slave device. The master die includes a master device, one or more bus-side WBIs coupled to the master device. Each bus-side WBI is configured to be wirelessly coupled to at least one slave-side WBI of the one or more slave dies and a system bus. The system bus includes the one or more bus-side WBIs and the slave-side WBIs of the one or more slave-side dies. The system bus is configured to exchange information between the master device and the slave devices of the one or more slave dies.

10. 发明申请

WO2020016550A1 MEMORY SCANNING OPERATION IN RESPONSE TO COMMON MODE FAULT SIGNAL 审中-公开
公开(公告)号：WO2020016550A1
公开(公告)日：2020-01-23
申请号：PCT/GB2019/051570
申请日：2019-06-06
申请人： ARM LIMITED
发明人： MERIAC, Milosch , ÖZER, Emre , ITURBE, Xabier , VENU, Balaji , DAS, Shidhartha
IPC分类号： G06F11/07 , G06F11/16
摘要： An apparatus comprises a plurality of redundant processing units (4) to perform data processing redundantly in lockstep; common mode fault detection circuitry *6, 22) to detect an event indicative of a potential common mode fault affecting each of the plurality of redundant processing units; a memory (10) shared between the plurality of redundant processing units; and memory checking circuitry (30) to perform a memory scanning operation to scan at least part of the memory for errors; in which the memory checking circuitry (30) performs the memory scanning operation in response to a common mode fault signal generated by the common mode fault detection circuitry (6, 22) indicating that the event indicative of a potential common mode fault has been detected.

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