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1. 发明申请

WO2007019222A2 HIGH-SPEED SERIAL DATA RECEIVER ARCHITECTURE 审中-公开
标题翻译：高速串行数据接收机架构
公开(公告)号：WO2007019222A2
公开(公告)日：2007-02-15
申请号：PCT/US2006030248
申请日：2006-08-02
申请人： ALTERA CORP , TRAN THUNGOC M , SHUMARAYEV SERGEY YURYEVICH , MAANGAT SIMARDEEP , WONG WILSON , PATEL RAKESH
发明人： TRAN THUNGOC M , SHUMARAYEV SERGEY YURYEVICH , MAANGAT SIMARDEEP , WONG WILSON , PATEL RAKESH
IPC分类号： H04L25/03
CPC分类号： H04L1/243 , H04L25/03878
摘要： Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.
摘要翻译：用于包含在PLD中的串行数据信号接收器电路包括串联连接并且可单独控制的多个均衡器电路，使得它们可以统一地补偿宽范围的可能的输入信号衰减特性。其他电路特征可以相对于均衡器电路连接以给予接收机电路其他能力。例如，这些其他特征可以包括各种类型的环回测试电路，可控终端电阻，可控共模电压以及用于检测输入信号的可控阈值。接收器电路的控制的各个方面可以是可编程的。

2. 发明专利

DE602006019184D1 Programmierbare Schaltung für die digitale Verstärkung und dazugehöriges Verfahren 未知
公开(公告)号：DE602006019184D1
公开(公告)日：2011-02-10
申请号：DE602006019184
申请日：2006-08-25
申请人： ALTERA CORP
发明人： LAI TIN , SHUMARAYEV SERGEY , MAANGAT SIMARDEEP , WONG WILSON
IPC分类号： H03G3/20 , H04L25/03

3. 发明专利

AT493793T 未知
公开(公告)号：AT493793T
公开(公告)日：2011-01-15
申请号：AT06017779
申请日：2006-08-25
申请人： ALTERA CORP
发明人： LAI TIN , SHUMARAYEV SERGEY , MAANGAT SIMARDEEP , WONG WILSON
IPC分类号： H03G3/20 , H04L25/03
摘要： Equalization circuitry may be used to compensate for the attenuation of a data signal caused by a transmission medium. The control circuitry for the equalization circuitry may generate control inputs for equalization stages that control the amount of gain provided to the data signal. A comparator may determine whether the gain from the equalization circuitry is less than or more than the desired amount of gain. A programmable up/down counter may adjust the counter value based on the output of the comparator. The counter value may be converted into one or more analog voltages using one or more digital-to-analog converters. These analog voltages may be provided to the equalization stages as control inputs. The control circuitry may also include hysteresis circuitry that prevents the counter value from being adjusted when the gain produced by the equalization stages is close to the desired amount of gain.

4. 发明专利

JP2008072716A Digital adaptation circuitry and method for programmable logic devices 审中-公开
标题翻译：数字适应电路和可编程逻辑器件的方法
公开(公告)号：JP2008072716A
公开(公告)日：2008-03-27
申请号：JP2007237202
申请日：2007-09-12
申请人： Altera Corp , アルテラコーポレイションAltera Corporation
发明人： WONG WILSON , CHAN DORIS PO CHING , SHUMARAYEV SERGEY , MAANGAT SIMARDEEP , HOANG TIM TRI , LAI TIN H , TRAN THUNGOC M
IPC分类号： H04B3/14 , H04B3/06 , H04L25/03
CPC分类号： H04L25/03885
摘要： PROBLEM TO BE SOLVED: To provide digital adaptation circuitry and method for programmable logic devices.
SOLUTION: This method provides for controlling equalization of an incoming data signal. The method includes detecting two successive differently valued bits in the data signal, determining whether transition in the incoming data signal between those bits occurs relatively late or relatively early, and increasing the equalization of the incoming data signal if it is relatively late.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为可编程逻辑器件提供数字适配电路和方法。解决方案：该方法用于控制输入数据信号的均衡。该方法包括检测数据信号中的两个连续的不同值的位，确定这些位之间的输入数据信号中的转换是否相对较晚或相对较早地发生，如果相对较晚，则增加输入数据信号的均衡。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2012199545A Low-voltage reference circuit 有权
标题翻译：低电压参考电路
公开(公告)号：JP2012199545A
公开(公告)日：2012-10-18
申请号：JP2012056840
申请日：2012-03-14
申请人： Altera Corp , アルテラコーポレイションAltera Corporation
发明人： ALBERT RATNAKUMAR , XIANG QI , MAANGAT SIMARDEEP , JUN LIU
IPC分类号： H01L27/04 , G05F3/30 , H01L21/329 , H01L21/822 , H01L29/88 , H01L29/94
CPC分类号： G05F3/30
摘要： PROBLEM TO BE SOLVED: To provide a reference circuit which operates with a low voltage.SOLUTION: A low-voltage reference circuit can comprise a pair of semiconductor devices. Each of the semiconductor devices can include an n-type semiconductor region, an n+ region in the n-type semiconductor region, a metal gate, and a gate insulator. The gate insulator is inserted between the metal gate and the n-type semiconductor region, and carriers tunnel through the metal gate and the n-type semiconductor region. The metal gate can have a work function which matches a work function of a p-type polysilicon. The gate insulator can have a thickness smaller than approximately 25 angstroms. The metal gate can form a first terminal in the semiconductor device. The n+ region and the n-type semiconductor region can form a second terminal in the semiconductor device. The second terminal can be coupled to the ground. A bias circuit can use the first terminal so as to supply a different current to the semiconductor device, and can supply a corresponding reference output voltage at a value less than 1 volt.
摘要翻译：要解决的问题：提供以低电压工作的参考电路。解决方案：低压参考电路可以包括一对半导体器件。每个半导体器件可以包括n型半导体区域，n型半导体区域中的n +区域，金属栅极和栅极绝缘体。栅极绝缘体插入在金属栅极和n型半导体区域之间，并且载流子穿过金属栅极和n型半导体区域。金属栅极可以具有匹配p型多晶硅的功函数的功函数。栅极绝缘体可以具有小于约25埃的厚度。金属栅极可以在半导体器件中形成第一端子。 n +区域和n型半导体区域可以在半导体器件中形成第二端子。第二个终端可以耦合到地面。偏置电路可以使用第一端子以向半导体器件提供不同的电流，并且可以以小于1伏的值提供相应的参考输出电压。版权所有（C）2013，JPO＆INPIT

6. 发明专利

JP2011103678A Digital adaptation circuitry and method for programmable logic device 有权
标题翻译：数字适配电路和可编程逻辑器件的方法
公开(公告)号：JP2011103678A
公开(公告)日：2011-05-26
申请号：JP2010291281
申请日：2010-12-27
申请人： Altera Corp , アルテラコーポレイションAltera Corporation
发明人： WONG WILSON , CHAN DORIS PO CHING , SHUMARAYEV SERGEY , MAANGAT SIMARDEEP , HOANG TIM TRI , LAI TIN H , TRAN THUNGOC M
IPC分类号： H04B3/04 , H04L25/03
CPC分类号： H04L25/03885
摘要： PROBLEM TO BE SOLVED: To provide a digital adaptation circuitry and method for a programmable logic device. SOLUTION: A method of controlling equalization of an incoming data signal includes: detecting two continuous bits having different values in the data signal; determining whether transition in the incoming data signal between the two bits is relatively slow or relatively fast; and increasing the equalization of the incoming data signal when the transition is relatively slow. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为可编程逻辑器件提供数字适配电路和方法。控制输入数据信号的均衡的方法包括：检测数据信号中具有不同值的两个连续位; 确定两个位之间的输入数据信号中的转换是相对较慢还是相对较快; 并且当转换相对较慢时，增加输入数据信号的均衡。版权所有（C）2011，JPO＆INPIT

7. 发明专利

JP2007097160A Programmable digital control equalization circuitry and method 审中-公开
标题翻译：可编程数字控制均衡电路和方法
公开(公告)号：JP2007097160A
公开(公告)日：2007-04-12
申请号：JP2006240927
申请日：2006-09-06
申请人： Altera Corp , アルテラコーポレイションAltera Corporation
发明人： LAI TIN , SHUMARAYEV SERGEY , MAANGAT SIMARDEEP , WONG WILSON
IPC分类号： H04B3/06
CPC分类号： H03G3/3089 , H04L25/03885
摘要： PROBLEM TO BE SOLVED: To accurately adjust the amount of gain in equalization circuitry. SOLUTION: Equalization circuitry (200) may be used to compensate for the attenuation of a data signal caused by a transmission medium. The control circuitry for the equalization circuitry may generate control inputs for equalization stages (202) that control the amount of gain provided to the data signal. A comparator (212) may determine whether the gain from the equalization circuitry is less than or more than the desired amount of gain. A programmable up/down counter (204) may adjust the counter value based on the output of the comparator. The counter value may be converted into one or more analog voltages using one or more digital-to-analog converters (208, 210). The analog voltages may be provided to the equalization stages as control inputs. The control circuitry may also include hysteresis circuitry (214) that prevents the counter value from being adjusted when the gain produced by the equalization stages is close to the desired amount of gain. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：准确调整均衡电路中的增益量。解决方案：均衡电路（200）可用于补偿由传输介质引起的数据信号的衰减。用于均衡电路的控制电路可以产生用于控制提供给数据信号的增益量的均衡级（202）的控制输入。比较器（212）可以确定来自均衡电路的增益是否小于或大于期望的增益量。可编程上/下计数器（204）可以基于比较器的输出来调整计数器值。可以使用一个或多个数模转换器（208,210）将计数器值转换成一个或多个模拟电压。模拟电压可以作为控制输入提供给均衡级。控制电路还可以包括滞后电路（214），当由均衡级产生的增益接近期望的增益量时，阻止计数器值被调整。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2012130047A Programmable receiver equalization circuit and method 有权
标题翻译：可编程接收器均衡电路和方法
公开(公告)号：JP2012130047A
公开(公告)日：2012-07-05
申请号：JP2012022868
申请日：2012-02-06
申请人： Altera Corp , アルテラコーポレイションAltera Corporation
发明人： MAANGAT SIMARDEEP , SHUMARAYEV SERGEY , WONG WILSON , TU NGOC TRAN
IPC分类号： H04B3/04 , H04L25/02 , H04L25/03
CPC分类号： H04L25/03885 , H04B3/04 , H04L25/03019
摘要： PROBLEM TO BE SOLVED: To provide an equalization circuit for appropriately compensating for attenuation caused by transmission media.SOLUTION: Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. An equalization circuit (106) includes a plurality of stages (202) arranged in series to allow frequency responses of the stages (202) to be integrated together. Each stage (202) is programmable to insert a zero, thus causing the frequency response of the stage (202) to be increased in magnitude by 20 dB/decade. The frequency location of zero is also programmable to allow each stage (202) to contribute to a certain amount of a gain for a specific frequency. Each stage (202) is also programmable to determine the location of a pole for the reduction of high frequency noise and cross-talk cancellation.
摘要翻译：要解决的问题：提供用于适当地补偿由传输介质引起的衰减的均衡电路。解决方案：通过传输介质传输的数据信号受到传输介质所造成的衰减。均衡电路（106）包括串联布置的多个级（202），以允许级（202）的频率响应被集成在一起。每个级（202）可编程为插入零，从而使得级（202）的频率响应在幅度上增加20dB /十倍。零的频率位置也是可编程的，以允许每个级（202）为特定频率贡献一定量的增益。每个级（202）也是可编程的，以确定用于降低高频噪声和串扰消除的极点的位置。版权所有（C）2012，JPO＆INPIT

9. 发明专利

JP2007028625A Programmable receiver equalization circuit and method 有权
标题翻译：可编程接收器均衡电路和方法
公开(公告)号：JP2007028625A
公开(公告)日：2007-02-01
申请号：JP2006193262
申请日：2006-07-13
申请人： Altera Corp , アルテラコーポレイションAltera Corporation
发明人： MAANGAT SIMARDEEP , SHUMARAYEV SERGEY , WONG WILSON , TRAN THUNGOC
IPC分类号： H04B3/04 , H04L25/03
CPC分类号： H04L25/03885 , H04B3/04 , H04L25/03019
摘要： PROBLEM TO BE SOLVED: To provide an equalization circuit for appropriately compensating for attenuation caused by transmission media.
SOLUTION: Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. Equalization circuitry (106) may include a plurality of stages (202) arranged in series to allow frequency responses of the stages (202) to be aggregated together. Each stage (202) may be programmable to insert a zero, thus causing the frequency response of the stage (202) to be increased in magnitude by 20 dB/decade. The frequency location of zero may also be programmable to allow each stage (202) to contribute to a certain amount of a gain for a specific frequency. Each stage (202) may also be programmable to determine the location of a pole for the reduction of high frequency noise and cross-talk cancellation.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供用于适当地补偿由传输介质引起的衰减的均衡电路。解决方案：通过传输介质传输的数据信号受到传输介质所造成的衰减。均衡电路（106）可以包括串联布置的多个级（202），以允许级（202）的频率响应聚合在一起。每个级（202）可以是可编程的以插入零，从而使得级（202）的频率响应在幅度上增加20dB /十倍。零的频率位置也可以是可编程的，以允许每个级（202）为特定频率贡献一定量的增益。每个级（202）也可以被编程以确定用于降低高频噪声和串扰消除的极点的位置。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2014064328A Digital adaptive circuit network and method for programmable logic device 有权
标题翻译：数字自适应电路网络和可编程逻辑器件的方法
公开(公告)号：JP2014064328A
公开(公告)日：2014-04-10
申请号：JP2013268773
申请日：2013-12-26
申请人： Altera Corp , アルテラコーポレイションAltera Corporation
发明人： WONG WILSON , CHAN DORIS PO CHING , SHUMARAYEV SERGEY , MAANGAT SIMARDEEP , HOANG TIM TRI , LAI TIN H , TRAN THUNGOC M
IPC分类号： H04L25/03 , H04B3/04
CPC分类号： H04L25/03885
摘要： PROBLEM TO BE SOLVED: To provide a digital adaptive circuit network and a method for a programmable logic device.SOLUTION: A method controls equalization of an incoming data signal. The method comprises steps of: detecting bits having two consecutive different values out of the data signal; determining whether transition in the incoming data signal between the two bits is relatively low in speed or relatively high in speed; and increasing the equalization of the incoming data signal when the transition is relatively low in speed.
摘要翻译：要解决的问题：提供数字自适应电路网络和可编程逻辑器件的方法。解决方案：一种控制输入数据信号的均衡的方法。该方法包括以下步骤：从数据信号中检测具有两个连续不同值的位; 确定两个比特之间的输入数据信号中的转换是相对低的速度还是相对较高的速度; 并且当转换速度相对较低时，增加输入数据信号的均衡。

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