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1. 发明申请

WO2010040144A1 MULTI-PROCESSOR ARCHITECTURE AND METHOD 审中-公开
标题翻译：多处理器架构和方法
公开(公告)号：WO2010040144A1
公开(公告)日：2010-04-08
申请号：PCT/US2009/059594
申请日：2009-10-05
申请人： ADVANCED MICRO DEVICES, INC. , SOLKI, Shahin , MOREIN, Stephen , GROSSMAN, Mark, S.
发明人： SOLKI, Shahin , MOREIN, Stephen , GROSSMAN, Mark, S.
IPC分类号： G06F3/14 , G06F13/42 , G06F1/32
CPC分类号： G06F13/4282 , G06F3/14 , G06F2213/0026 , G06T1/20 , G06T1/60 , G09G5/006 , G09G5/363 , G09G2330/021 , G09G2360/06
摘要： Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC Embodiments are usable with known bus protocols.
摘要翻译：本文描述了多处理器架构和方法的实施例。实施例提供了使用外部桥式集成电路（IC）架构的替代方案。例如，实施例复用外围总线，使得多个处理器可以使用一个外围接口时隙而不需要外部桥IC实施例可用于已知的总线协议。

2. 发明申请

WO2009123933A1 PEER-TO-PEER SPECIAL PURPOSE PROCESSOR ARCHITECTURE AND METHOD 审中-公开
标题翻译：同行对应的特殊用途处理器架构和方法
公开(公告)号：WO2009123933A1
公开(公告)日：2009-10-08
申请号：PCT/US2009/038637
申请日：2009-03-27
申请人： ADVANCED MICRO DEVICES, INC. , MOREIN, Stephen , GROSSMAN, Mark, S. , KRUGER, Warren, Fritz , ETSCHEID, Brian
发明人： MOREIN, Stephen , GROSSMAN, Mark, S. , KRUGER, Warren, Fritz , ETSCHEID, Brian
IPC分类号： G06F13/42 , G06F15/163
CPC分类号： G06F13/4265 , G06F15/163 , G06F2213/0026
摘要： A peer-to-peer special purpose processor architecture and method is described, Embodiments include a plurality of special purpose processors coupled to a central processing unit via a host bridge bus, a direct bus directly coupling each of the plurality of special purpose processors to at least one other of the plurality of special purpose processors and a memory controller coupled to the plurality of special purpose processors, wherein the at least one memory controller determines whether to transmit data via the host bus or the direct bus, and whether to receive data via the host bus or the direct bus.
摘要翻译：描述了对等专用处理器架构和方法，实施例包括经由主桥总线耦合到中央处理单元的多个专用处理器，将多个专用处理器中的每一个直接耦合到所述多个专用处理器中的至少另一个以及耦合到所述多个专用处理器的存储器控制器，其中所述至少一个存储器控制器确定是经由所述主机总线还是直接总线发送数据，以及是否经由主机总线或直接总线。

3. 发明申请

WO2007054808A2 ERROR DETECTION IN HIGH SPEED ASYMMETRIC INTERFACES USING DEDICATED INTERFACE LINES 审中-公开
标题翻译：高速不对称接口中使用专用接口线的误差检测
公开(公告)号：WO2007054808A2
公开(公告)日：2007-05-18
申请号：PCT/IB2006/003180
申请日：2006-11-10
申请人： ADVANCED MICRO DEVICES, INC , MACRI, Joseph , MOREIN, Stephen , GAUTHIER, Claude , LEE, Ming-Ju, E. , CHEN, Lin
发明人： MACRI, Joseph , MOREIN, Stephen , GAUTHIER, Claude , LEE, Ming-Ju, E. , CHEN, Lin
IPC分类号： H04L1/00 , G06F11/08
CPC分类号： H04L1/0045 , G06F11/08 , G06F11/10 , H04L1/0061 , H04L2001/0094
摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.
摘要翻译：描述了用于检测高速不对称接口中的错误的系统和方法。实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件明显比第二组件更智能。第一个组件通过接口的一行接收来自第二个组件的签名，并通过该接口进行READ和WRITE操作。与从第二组件到第一组件签名的传输相关联的等待时间是第二组件计算签名所用的时间。将收到的签名与第一个组件存储的签名进行比较。这两个签名都对应于特定的READ或WRITE命令。基于比较，第一个组件确定READ或WRITE操作是否成功，并根据需要指示第二个组件。

4. 发明申请

WO2007052147A3 ERROR DETECTION IN HIGH SPEED ASYMMETRIC INTERFACES 审中-公开
公开(公告)号：WO2007052147A3
公开(公告)日：2007-05-10
申请号：PCT/IB2006/003113
申请日：2006-11-02
申请人： ADVANCED MICRO DEVICES, INC. , MACRI, Joseph , MOREIN, Stephen , GAUTHIER, Claude , LEE, Ming-Ju, E. , CHEN, Lin
发明人： MACRI, Joseph , MOREIN, Stephen , GAUTHIER, Claude , LEE, Ming-Ju, E. , CHEN, Lin
IPC分类号： G06F11/10
摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.

5. 发明授权

EP2342626B1 MULTI-PROCESSOR ARCHITECTURE AND METHOD 有权转让
标题翻译：更多处理器架构和方法
公开(公告)号：EP2342626B1
公开(公告)日：2015-07-08
申请号：EP09737270.0
申请日：2009-10-05
申请人： Advanced Micro Devices, Inc. , ATI Technologies ULC
发明人： SOLKI, Shahin , MOREIN, Stephen , GROSSMAN, Mark, S.
IPC分类号： G06F3/14 , G06F13/42 , G06F1/32
CPC分类号： G06F13/4282 , G06F3/14 , G06F2213/0026 , G06T1/20 , G06T1/60 , G09G5/006 , G09G5/363 , G09G2330/021 , G09G2360/06
摘要： Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.

6. 发明公开

EP2342626A1 MULTI-PROCESSOR ARCHITECTURE AND METHOD 有权转让
标题翻译：更多处理器架构和方法
公开(公告)号：EP2342626A1
公开(公告)日：2011-07-13
申请号：EP09737270.0
申请日：2009-10-05
申请人： Advanced Micro Devices, Inc.
发明人： SOLKI, Shahin , MOREIN, Stephen , GROSSMAN, Mark, S.
IPC分类号： G06F3/14 , G06F13/42 , G06F1/32
CPC分类号： G06F13/4282 , G06F3/14 , G06F2213/0026 , G06T1/20 , G06T1/60 , G09G5/006 , G09G5/363 , G09G2330/021 , G09G2360/06
摘要： Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.

7. 发明授权

EP2260394B1 PEER-TO-PEER SPECIAL PURPOSE PROCESSOR ARCHITECTURE AND METHOD 有权
标题翻译：对等网络处理器架构适用于特定用途及相应方法
公开(公告)号：EP2260394B1
公开(公告)日：2014-08-13
申请号：EP09727019.3
申请日：2009-03-27
申请人： Advanced Micro Devices, Inc.
发明人： MOREIN, Stephen , GROSSMAN, Mark, S. , KRUGER, Warren, Fritz , ETSCHEID, Brian
IPC分类号： G06F13/42 , G06F15/163
CPC分类号： G06F13/4265 , G06F15/163 , G06F2213/0026

8. 发明公开

EP1955467A2 ERROR DETECTION IN HIGH SPEED ASYMMETRIC INTERFACES USING DEDICATED INTERFACE LINES 审中-公开
标题翻译：快速，非对称接口错误检测使用特殊的接口线
公开(公告)号：EP1955467A2
公开(公告)日：2008-08-13
申请号：EP06809206.3
申请日：2006-11-10
申请人： ADVANCED MICRO DEVICES, INC.
发明人： MACRI, Joseph , MOREIN, Stephen , GAUTHIER, Claude , LEE, Ming-Ju, E. , CHEN, Lin
IPC分类号： H04L1/00 , G06F11/08
CPC分类号： H04L1/0045 , G06F11/08 , G06F11/10 , H04L1/0061 , H04L2001/0094
摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.

9. 发明公开

EP2260394A1 PEER-TO-PEER SPECIAL PURPOSE PROCESSOR ARCHITECTURE AND METHOD 有权
标题翻译：对等网络处理器架构适用于特定用途及相应方法
公开(公告)号：EP2260394A1
公开(公告)日：2010-12-15
申请号：EP09727019.3
申请日：2009-03-27
申请人： Advanced Micro Devices, Inc.
发明人： MOREIN, Stephen , GROSSMAN, Mark, S. , KRUGER, Warren, Fritz , ETSCHEID, Brian
IPC分类号： G06F13/42 , G06F15/163
CPC分类号： G06F13/4265 , G06F15/163 , G06F2213/0026
摘要： A peer-to-peer special purpose processor architecture and method is described, Embodiments include a plurality of special purpose processors coupled to a central processing unit via a host bridge bus, a direct bus directly coupling each of the plurality of special purpose processors to at least one other of the plurality of special purpose processors and a memory controller coupled to the plurality of special purpose processors, wherein the at least one memory controller determines whether to transmit data via the host bus or the direct bus, and whether to receive data via the host bus or the direct bus.

10. 发明公开

EP1955163A2 ERROR DETECTION IN HIGH SPEED ASYMMETRIC INTERFACES 审中-公开
标题翻译： SCHNELLEN不寻常的SCHNITTSTELLEN的FEHLERDETION
公开(公告)号：EP1955163A2
公开(公告)日：2008-08-13
申请号：EP06809185.9
申请日：2006-11-02
申请人： ADVANCED MICRO DEVICES, INC.
发明人： MACRI, Joseph , MOREIN, Stephen , GAUTHIER, Claude , LEE, Ming-Ju, E. , CHEN, Lin
IPC分类号： G06F11/10
CPC分类号： G06F11/10
摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.
摘要翻译：描述了用于检测高速非对称接口中的错误的系统和方法。实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。第一个组件控制第二个组件的许多操作，包括通过接口的现有行接收来自第二个组件的签名。所接收的签名与由第一组件存储的签名进行比较。两个签名对应于接口上的事务。基于比较，第一个组件确定事务是否成功，并根据需要指示第二个组件。

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