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1. 发明授权

US6118699A Semiconductor memory device using MONOS type nonvolatile memory cell 失效
标题翻译：半导体存储器件采用MONOS型非易失性存储单元
公开(公告)号：US6118699A
公开(公告)日：2000-09-12
申请号：US352838
申请日：1999-07-13
申请人： Yuuichi Tatsumi , Noriaki Suzuki , Hidenobu Minagawa , Kazuhiko Satou , Hitoshi Ohta
发明人： Yuuichi Tatsumi , Noriaki Suzuki , Hidenobu Minagawa , Kazuhiko Satou , Hitoshi Ohta
IPC分类号： H01L27/115 , G11C16/04
CPC分类号： G11C16/0416 , H01L27/115
摘要： That surface portion of a semiconductor substrate which is adjacent to a buried source region formed in the substrate is covered with an offset side wall to suppress expansion of a channel beneath the offset side wall. In addition, buried source regions in the form of offset side walls are formed on the two sides of a drain region having one non-offset side wall to prevent a write or read error in unselected memory cell transistors on both sides of a selected memory transistor either in a data write or in a data read.
摘要翻译：与形成在基板中的埋入源极区域相邻的半导体基板的表面部分被偏移侧壁覆盖，以抑制偏移侧壁下方的通道的膨胀。此外，在具有一个非偏移侧壁的漏极区域的两侧上形成有偏移侧壁形式的掩埋源极区域，以防止选定存储晶体管两侧的未选择的存储单元晶体管中的写入或读取错误在数据写入或数据读取中。

2. 发明授权

US6014443A Semiconductor memory device having copy protect function and method for accessing the same 失效
标题翻译：具有复制保护功能的半导体存储器件及其访问方法
公开(公告)号：US6014443A
公开(公告)日：2000-01-11
申请号：US859682
申请日：1997-05-20
申请人： Yoshio Mochizuki , Yuuichi Tatsumi
发明人： Yoshio Mochizuki , Yuuichi Tatsumi
IPC分类号： G06F12/14 , G06F21/24 , G11C17/00 , H04L9/00
CPC分类号： G06F12/1408
摘要： Cryptographic key data and data subjected to an operation by use of the cryptographic key data are previously stored in a memory cell array. A memory cell in which the cryptographic key data is stored is accessed and latched and the cryptographic key data is latched in a latch circuit before read out data from the memory cell array. After this, the latched data and data output from a sense amplifier are subjected to an operation by an arithmetical circuit to decode the data and the result of the operation is output as readout data.
摘要翻译：加密密钥数据和使用加密密钥数据进行操作的数据预先存储在存储单元阵列中。在从存储单元阵列读出数据之前，访问和锁存其中存储密码密钥数据的存储单元，并将锁密钥数据锁存在锁存电路中。此后，从读出放大器输出的锁存数据和数据经过算术电路进行操作，对数据进行解码，并将该操作结果作为读出数据输出。

3. 发明授权

US4916334A High voltage booster circuit for use in EEPROMs 失效
标题翻译：用于EEPROM的高压升压电路
公开(公告)号：US4916334A
公开(公告)日：1990-04-10
申请号：US226312
申请日：1988-07-29
申请人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Mizuho Imai
发明人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Mizuho Imai
IPC分类号： G11C16/30 , H02M3/07 , H03K5/02
CPC分类号： G11C16/30 , H02M3/07 , H03K5/023
摘要： A semiconductor integrated circuit includes a CMOS circuit operated on a voltage of a first voltage level to set an output node thereof to a voltage of the first voltage level or a reference voltage; an output circuit for controlling supply of a voltage of a second voltage level which is higher than the first voltage level to a signal output node; and an isolation MOS transistor having a current path connected between the output node of the CMOS circuit and the signal output node and a gate connected to receive a control signal. The output node of the CMOS circuit is set to the reference voltage with the conduction resistance of the isolation MOS transistor kept high after the lapse of period in which the voltage of the second voltage level is kept supplied to the signal output node. After this, the conduction resistance of the isolation MOS transistor is reduced in response to the control signal.
摘要翻译：半导体集成电路包括以第一电压电平工作的CMOS电路，以将其输出节点设置为第一电压电平或参考电压的电压; 输出电路，用于控制向信号输出节点提供高于第一电压电平的第二电压电平的电压; 以及隔离MOS晶体管，其具有连接在CMOS电路的输出节点和信号输出节点之间的电流路径以及连接以接收控制信号的栅极。 CMOS电路的输出节点被设定为参考电压，其中隔离MOS晶体管的导通电阻保持高电平，其中第二电压电平的电压被保持提供给信号输出节点。此后，隔离MOS晶体管的导通电阻响应于控制信号而减小。

4. 发明申请

US20060166384A1 Method for manufacturing industrial products and combination of masks for manufacturing the same 失效
标题翻译：制造工业产品的方法和制造掩模的组合
公开(公告)号：US20060166384A1
公开(公告)日：2006-07-27
申请号：US11325545
申请日：2006-01-05
申请人： Yuuichi Tatsumi
发明人： Yuuichi Tatsumi
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： H01L22/22 , G01R31/2853 , H01L22/32 , H01L2224/05553
摘要： A method for manufacturing an industrial product encompasses: forming a intermediate product pattern, which implements a part of a intermediate product of the industrial product by a sequence of processes corresponds to a part of a procedure for manufacturing the industrial product; forming an interconnect-changing insulator on the intermediate product pattern; boring sampling contact holes in the interconnect-changing insulator so as to make bare a part of the intermediate product pattern to define sampling sites; delineating evaluation interconnects on the interconnect-changing insulator so that each of the evaluation interconnects can electrically connected to at least one of the sampling sites of intermediate product pattern; and measuring an electrical resistance between subject sampling sites through the evaluation interconnects so as to detect a product defect in the intermediate product pattern.
摘要翻译：一种制造工业产品的方法包括：形成中间产品图案，其通过一系列工艺实现工业产品的中间产品的一部分对应于制造工业产品的程序的一部分; 在所述中间产品图案上形成互连变换绝缘体; 在互连变换绝缘体中的无孔采样接触孔，以便露出中间产品图案的一部分以限定取样位置; 描绘互连变换绝缘体上的评估互连，使得每个评估互连可以电连接到中间产品图案的至少一个采样点; 以及通过评估互连测量被检体取样部位之间的电阻，以便检测中间产品图案中的产品缺陷。

5. 发明授权

US4882507A Output circuit of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的输出电路
公开(公告)号：US4882507A
公开(公告)日：1989-11-21
申请号：US226307
申请日：1988-07-29
申请人： Yuuichi Tatsumi , Hidenobu Minagawa , Hiroshi Iwahashi , Masamichi Asano , Mizuho Imai
发明人： Yuuichi Tatsumi , Hidenobu Minagawa , Hiroshi Iwahashi , Masamichi Asano , Mizuho Imai
IPC分类号： G11C11/417 , G11C7/10 , G11C7/22 , G11C11/409 , G11C17/18 , H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/0185
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/22 , H03K19/00361
摘要： A semiconductor integrated circuit includes an output circuit and a control circuit for controlling the output circuit. The control circuit controls the output circuit so as to charge or discharge a preset node in the output circuit at a rate different from an ordinary charging or discharging rate for a preset period of time after a control signal has been changed in level.

6. 发明授权

US4858192A Semiconductor memory device with redundancy circuit 失效
标题翻译：具有冗余电路的半导体存储器件
公开(公告)号：US4858192A
公开(公告)日：1989-08-15
申请号：US225510
申请日：1988-07-28
申请人： Yuuichi Tatsumi , Hidenobu Minagawa , Hiroshi Iwahashi , Masamichi Asano , Mizuho Imai
发明人： Yuuichi Tatsumi , Hidenobu Minagawa , Hiroshi Iwahashi , Masamichi Asano , Mizuho Imai
IPC分类号： G11C17/00 , G11C16/06 , G11C29/00 , G11C29/04
CPC分类号： G11C29/781
摘要： A semiconductor memory device has a redundancy circuit for compensating a defective bit when it occurs in the main memory cells. The redundancy circuit includes spare memory cells, a spare row decoder for selecting the spare memory cells, a first circuit section for inhibiting the use of the main row decoder when the spare row decoder is used, and a second circuit section for selecting the spare row decoder when an address specifying the main row line connected to the defective memory cell is denoted.
摘要翻译：半导体存储器件具有用于在发生在主存储器单元中时补偿有缺陷的位的冗余电路。冗余电路包括备用存储单元，用于选择备用存储单元的备用排解码器，当使用备用行解码器时禁止使用主行解码器的第一电路部分和用于选择备用行的第二电路部分解码器，当指定连接到有缺陷的存储单元的主行线的地址被表示时。

7. 发明授权

US06376295B1 Method for manufacturing a semiconductor memory device with a fine structure 失效
标题翻译：具有精细结构的半导体存储器件的制造方法
公开(公告)号：US06376295B1
公开(公告)日：2002-04-23
申请号：US09631977
申请日：2000-08-03
申请人： Kiyomi Naruke , Minoru Kurata , Yuuichi Tatsumi , Yasumasa Sawada
发明人： Kiyomi Naruke , Minoru Kurata , Yuuichi Tatsumi , Yasumasa Sawada
IPC分类号： H01L218238
CPC分类号： H01L27/11568 , G11C16/0491 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546
摘要： There is disclosed a memory cell which has a diffusion layers constituting source/drain areas formed on a p-type silicon substrate surface, and a channel area formed between the diffusion layers. Above the channel area, an insulating film of a laminated structure is formed of a silicon oxide film, a silicon nitride film and a silicon oxide film. A gate electrode is formed on the upper surface of the insulating film of the laminated structure. The gate electrode is used as a word line. Moreover, an interlayer insulating film is formed between the diffusion layer and the gate electrode. By injecting hot electrons from the substrate to the silicon nitride film in the insulating film of the laminated structure, data is written. The silicon nitride film and the diffusion layer are partially overlapped in a vertical direction, and an offset portion is disposed between the silicon nitride film and the diffusion layer.
摘要翻译：公开了一种存储单元，其具有构成在p型硅衬底表面上形成的源/漏区的扩散层和形成在扩散层之间的沟道区。在通道区域之上，层叠结构的绝缘膜由氧化硅膜，氮化硅膜和氧化硅膜形成。在层叠结构体的绝缘膜的上表面上形成栅电极。栅电极用作字线。此外，在扩散层和栅电极之间形成层间绝缘膜。通过将层叠结构的绝缘膜中的热电子从基板注入氮化硅膜，写入数据。氮化硅膜和扩散层在垂直方向上部分重叠，偏移部分设置在氮化硅膜和扩散层之间。

8. 发明授权

US5175704A Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5175704A
公开(公告)日：1992-12-29
申请号：US607468
申请日：1990-10-31
申请人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Hiroto Nakai , Mizuho Imai
发明人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Hiroto Nakai , Mizuho Imai
IPC分类号： G11C16/10 , G11C16/24 , G11C16/30 , G11C16/34
CPC分类号： G11C16/10 , G11C16/24 , G11C16/30 , G11C16/34
摘要： In a nonvolatile semiconductor memory device, a wiring layer is connected between a power source and a memory cell. Resistance of the wiring layer is larger than the on-resistance of a load transistor, so that the load transistor substantially determines the load characteristic. Therefore, the load characteristic curve is more gentle in inclination and more rectilinear in shape. This makes the data writing operation stable against a variance in the channel lengths of manufactured transistors forming the memory cells.
摘要翻译：在非易失性半导体存储器件中，布线层连接在电源和存储单元之间。布线层的电阻大于负载晶体管的导通电阻，负载晶体管基本上决定负载特性。因此，载荷特性曲线在倾斜度上更为平缓，形状更为直线。这使得数据写入操作对于形成存储单元的制造的晶体管的沟道长度的变化是稳定的。

9. 发明授权

US4967394A Semiconductor memory device having a test cell array 失效
标题翻译：具有测试单元阵列的半导体存储器件
公开(公告)号：US4967394A
公开(公告)日：1990-10-30
申请号：US241748
申请日：1988-09-08
申请人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Mizuho Imai
发明人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Mizuho Imai
IPC分类号： G11C16/08 , G11C16/28 , G11C16/32 , G11C16/34 , G11C29/24 , G11C29/50 , G11C29/52
CPC分类号： G11C29/50012 , G11C16/08 , G11C16/28 , G11C16/32 , G11C16/34 , G11C29/24 , G11C29/50 , G11C29/52 , G11C16/04
摘要： A semiconductor memory device in which data can be read out in response to an address signal comprises power source lines, a plurality of row and column conductive lines, a memory cell array including nonvolatile memory cells arranged in a matrix form of rows and columns and respectively connected to the plurality of row and column lines and the power source lines, a first selector circuit for generating a signal for selecting the row conductive lines in response to an address signal, a dummy row line, and a dummy memory cells each having a source, a drain and a control gate connected to the dummy row line. In the semiconductor memory device, one of paths between the source and the power source line and between the drain and the corresponding row line is closed and the other path is opened, and it further includes a second selector circuit for selectively generating a line selection signal for selecting one of the row conductive lines in response to an address signal and a dummy selection signal for selecting the dummy row line in response to the same address signal.

10. 发明授权

US08241999B2 Semiconductor device having a protection pattern with two element separation regions 有权
标题翻译：具有具有两个元件分离区域的保护图案的半导体器件
公开(公告)号：US08241999B2
公开(公告)日：2012-08-14
申请号：US12706056
申请日：2010-02-16
申请人： Takafumi Ikeda , Takahito Nakazawa , Hideaki Maekawa , Yuuichi Tatsumi , Toshifumi Minami
发明人： Takafumi Ikeda , Takahito Nakazawa , Hideaki Maekawa , Yuuichi Tatsumi , Toshifumi Minami
IPC分类号： H01L23/544 , H01L21/301
CPC分类号： H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a circuit element region formed on a semiconductor substrate, and a protective pattern formed so as to surround the circuit element region. The protective pattern comprises a first element separation region formed on the semiconductor substrate, a second element separation region formed on the semiconductor substrate and having a width smaller than that of the first element separation region, a first element region formed between the first element separation region and the second element separation region, a first gate layer formed on the first element separation region, a wiring layer formed on the first gate layer, a passivation layer formed above the wiring layer, a second element region, an insulation film formed on the second element region, and a second gate layer formed on the insulation film, the first element separation region, the first element region, the second element separation region and the second element region being located in this order from the nearer side of the circuit element region.
摘要翻译：半导体器件具有形成在半导体衬底上的电路元件区域和形成为围绕电路元件区域的保护图案。保护图案包括形成在半导体衬底上的第一元件分离区域，形成在半导体衬底上的第二元件分离区域，其宽度小于第一元件分离区域的宽度;第一元素区域，形成在第一元素分离区域和第二元件分离区域，形成在第一元件分离区域上的第一栅极层，形成在第一栅极层上的布线层，形成在布线层上方的钝化层，第二元素区域，形成在第二栅极层上的绝缘膜元件区域和形成在绝缘膜上的第二栅极层，第一元件分离区域，第一元件区域，第二元件分离区域和第二元件区域从电路元件区域的更靠近的方向定位。

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