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1. 发明授权

US08567228B2 Tool system with interchangeable tool inserts for punching machines 有权
标题翻译：刀具系统，具有用于冲孔机的可互换工具刀片
公开(公告)号：US08567228B2
公开(公告)日：2013-10-29
申请号：US12635279
申请日：2009-12-10
申请人： Stefan Buettner , Wolfgang Laib
发明人： Stefan Buettner , Wolfgang Laib
IPC分类号： B21D37/00
CPC分类号： B26F1/44 , B21D28/12 , B21D28/34 , B21D28/343 , B21D28/346 , B21D37/02 , B21D37/04 , B21D37/10 , B26F1/14 , Y10T83/8748 , Y10T83/9416 , Y10T83/9423 , Y10T83/9425 , Y10T83/97
摘要： A tool system is provided that has a stamp or punch adapter including eccentrically positioned stamp receptacles. This system permits a simple exchange of tool inserts in the stamp adapter. These tool inserts are also usable in another tool system. The system also permits combining the stamp adapter with a stamp shaft, which can also be used in another tool system. These features permit stamping (and punching) with minimal tooling and retooling efforts.
摘要翻译：提供了一种具有印模或冲头适配器的工具系统，其包括偏心定位的印字插座。该系统允许在印章适配器中简单地更换工具插入物。这些刀具刀片也可用于另一个刀具系统。该系统还允许将印章适配器与印章轴组合，该印章轴也可以用于另一个工具系统。这些功能允许冲压（和冲压），并以最小的工具和重新设计工具。

2. 发明申请

US20130128684A1 REDUCED LEAKAGE BANKED WORDLINE HEADER 审中-公开
标题翻译：减少泄漏银行字头
公开(公告)号：US20130128684A1
公开(公告)日：2013-05-23
申请号：US13466973
申请日：2012-05-08
申请人： Stefan Buettner , Thomas Froehnel , Werner Juchmes , Rolf Sautter , Victor Zyuban
发明人： Stefan Buettner , Thomas Froehnel , Werner Juchmes , Rolf Sautter , Victor Zyuban
IPC分类号： G11C5/14 , G11C8/10
CPC分类号： G11C5/14 , G11C8/08 , G11C8/10
摘要： A memory array can be arranged with header devices to reduce leakage. The header devices are coupled with a decoder to receive at least a first portion of a memory address indication and are coupled to receive current from a power supply. Each of header devices is adapted to provide power from the power supply to a set of the wordline drivers corresponding to a bank indicated with the first portion of the memory address indication. Each of the logic devices is coupled to receive at least a second portion of the memory address indication from a decoder. Each of the logic devices is coupled to activate the wordline drivers coupled with those of the wordlines indicated with the second portion of the memory address indication.
摘要翻译：存储器阵列可以配置有头部装置以减少泄漏。标题装置与解码器耦合以接收存储器地址指示的至少第一部分，并被耦合以从电源接收电流。每个头部装置适于从电源向与存储器地址指示的第一部分指示的存储体相对应的一组字线驱动器提供电力。每个逻辑设备被耦合以从解码器接收存储器地址指示的至少第二部分。每个逻辑设备被耦合以激活与由存储器地址指示的第二部分指示的字线的字线驱动器耦合的字线驱动器。

3. 发明授权

US07495949B2 Asymmetrical random access memory cell, memory comprising asymmetrical memory cells and method to operate such a memory 失效
标题翻译：不对称随机存取存储器单元，包括不对称存储单元的存储器和操作这种存储器的方法
公开(公告)号：US07495949B2
公开(公告)日：2009-02-24
申请号：US11669369
申请日：2007-01-31
申请人： Stefan Buettner , Torsten Mahnke , Wolfgang Penth , Otto Wagner
发明人： Stefan Buettner , Torsten Mahnke , Wolfgang Penth , Otto Wagner
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： An asymmetrical random access memory cell (1) including cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (blt, blc) of a pair of complementary bit-lines, which are connected via a pass-transistors (21, 31), wherein said cross coupled inverters (2, 3) have different switching thresholds and exhibit asymmetrical physical behaviours, wherein an additional pass-transistor (4) is provided in series to one of the pass-transistors (21) between one of the nodes (22) and its dedicated bit-line (blc). Further the invention relates to a random access memory including such memory cells and to a method of operating such a memory.
摘要翻译：包括交叉耦合的反相器（2,3）的非对称随机存取存储单元（1），它们通过一对互补位线的分开的位线（blt，blc）在它们的节点（22,32）处驱动，它们是通过传输晶体管（21,31）连接，其中所述交叉耦合的反相器（2,3）具有不同的开关阈值并且表现出不对称的物理行为，其中附加的传输晶体管（4）串联地提供给一个通过 - 晶体管（21）在其中一个节点（22）和其专用位线（blc）之间。此外，本发明涉及包括这种存储器单元的随机存取存储器以及操作这种存储器的方法。

4. 发明授权

US08499668B2 Discharging workpiece parts 有权
标题翻译：放电工件零件
公开(公告)号：US08499668B2
公开(公告)日：2013-08-06
申请号：US12581992
申请日：2009-10-20
申请人： Wolfgang Laib , Eric Schneider , Stefan Buettner
发明人： Wolfgang Laib , Eric Schneider , Stefan Buettner
IPC分类号： B62D7/00 , B26F1/14
CPC分类号： B21D28/14 , B21D28/34 , B21D45/003 , Y10T83/0448 , Y10T83/2216 , Y10T83/9425
摘要： A machine tool that includes a workpiece support and a punching die. The punching die includes a support surface, for supporting a workpiece to be processed, and a discharging slope. The discharging slope is configured such that a workpiece part, severed from a workpiece supported on the support surface of the punching die, is displaced, in at least one of a rotational, tilting, or linear movement, from a processing position at least partially overlying the discharging slope toward a removal position on the discharging slope. The discharging slope is also configured such that a workpiece part, severed from a workpiece supported on the support surface of the punching die, is directed, in a sliding movement, toward a discharging position located beneath the support surface and adjacent the punching die.
摘要翻译：一种机床，包括工件支撑件和冲压模具。冲压模具包括用于支撑待加工的工件的支撑表面和排出斜面。放电斜面被构造成使得从被支撑在冲压模具的支撑表面上的工件切断的工件部件以至少部分上覆的加工位置以旋转，倾斜或线性运动中的至少一个方式移位放电斜坡朝向放电斜坡上的去除位置。放电斜面还被构造成使得从被支撑在冲压模具的支撑表面上的工件切断的工件部件以滑动运动方向朝向位于支撑表面下方并与冲压模具相邻的排出位置。

5. 发明申请

US20120155188A1 REDUCED POWER CONSUMPTION MEMORY CIRCUITRY 失效
标题翻译：降低功耗记忆电路
公开(公告)号：US20120155188A1
公开(公告)日：2012-06-21
申请号：US13284480
申请日：2011-10-28
申请人： Stefan Buettner , David A. Hrusecky , Werner Juchmes , Wolfgang Penth , Rolf Sautter
发明人： Stefan Buettner , David A. Hrusecky , Werner Juchmes , Wolfgang Penth , Rolf Sautter
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/18 , G11C7/12 , G11C29/846 , G11C2207/005
摘要： In a circuit that reduces power consumption in an array system of memory cells accessible in parallel, a local evaluation circuit is connected to a memory cell and a global bit line of the array system of memory cells. A selection circuitry splits the global bit line into an upper part and a lower part of the global bit line. The selection circuitry is adapted to receive an early set prediction signal and to connect the upper part of the global bit line to the lower part of the global bit line based on the early set prediction signal. The early set prediction signal indicates whether a set of memory cells, which include the memory cell, is being read. The circuit also includes a N:1 multiplexer connected to the lower part of the global bit line to receive the lower part of the global bit line as input.
摘要翻译：在可以并行访问的存储单元的阵列系统中降低功耗的电路中，本地评估电路连接到存储器单元阵列系统的存储单元和全局位线。选择电路将全局位线分割成全局位线的上部和下部。选择电路适于接收早期设定的预测信号，并且基于早期设定的预测信号将全局位线的上部连接到全局位线的下部。早期设置的预测信号指示是否正在读取包括存储器单元的一组存储单元。该电路还包括连接到全局位线的下部的N：1多路复用器，以接收全局位线的下部作为输入。

6. 发明授权

US07844871B2 Test interface for memory elements 失效
标题翻译：测试界面的内存元素
公开(公告)号：US07844871B2
公开(公告)日：2010-11-30
申请号：US12268903
申请日：2008-11-11
申请人： Uwe Brandt , Stefan Buettner , Werner Juchmes , Juergen Pille
发明人： Uwe Brandt , Stefan Buettner , Werner Juchmes , Juergen Pille
IPC分类号： G01R31/28
CPC分类号： G11C29/16 , G11C29/32 , G11C2029/3202
摘要： A method for testing memory elements of an integrated circuit with an array built in self test (ABIST) comprises providing an ABIST interface to interface between an ABIST engine and a plurality of latches of a memory element under test, providing a multiplex (MUX) stage adjacent a scan input port of each latch, providing functional signal inputs to a data input port of the latches, setting the latches to an ABIST mode by activating an ABIST enable signal and delivering the ABIST enable signal to each of the latches, generating a plurality of ABIST test signals with the ABIST engine, applying the ABIST test signals in parallel to the scan input ports of the latches, determining whether one or more test patterns have been executed, and setting the latches to a normal run mode by deactivating the ABIST enable signal.
摘要翻译：一种用于测试具有内置于自检（ABIST）中的阵列的集成电路的存储器元件的方法，包括提供ABIST接口以在ABIST引擎和被测存储元件的多个锁存器之间进行接口，提供多路复用（MUX）级邻近每个锁存器的扫描输入端口，向锁存器的数据输入端口提供功能信号输入，通过激活ABIST使能信号并将ABIST使能信号传送到每个锁存器，将锁存器设置为ABIST模式，产生多个的ABIST测试信号与ABIST引擎并行地应用ABIST测试信号并且与锁存器的扫描输入端口并行，确定是否执行了一个或多个测试模式，并通过停用ABIST使能来将锁存器设置为正常运行模式信号。

7. 发明申请

US20100122128A1 TEST INTERFACE FOR MEMORY ELEMENTS 失效
标题翻译：记忆元素的测试界面
公开(公告)号：US20100122128A1
公开(公告)日：2010-05-13
申请号：US12268903
申请日：2008-11-11
申请人： Uwe Brandt , Stefan Buettner , Werner Juchmes , Juergen Pille
发明人： Uwe Brandt , Stefan Buettner , Werner Juchmes , Juergen Pille
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/16 , G11C29/32 , G11C2029/3202
摘要： A method for testing memory elements of an integrated circuit with an array built in self test (ABIST) comprises providing an ABIST interface to interface between an ABIST engine and a plurality of latches of a memory element under test, providing a multiplex (MUX) stage adjacent a scan input port of each latch, providing functional signal inputs to a data input port of the latches, setting the latches to an ABIST mode by activating an ABIST enable signal and delivering the ABIST enable signal to each of the latches, generating a plurality of ABIST test signals with the ABIST engine, applying the ABIST test signals in parallel to the scan input ports of the latches, determining whether one or more test patterns have been executed, and setting the latches to a normal run mode by deactivating the ABIST enable signal.
摘要翻译：一种用于测试具有内置于自检（ABIST）中的阵列的集成电路的存储器元件的方法，包括提供ABIST接口以在ABIST引擎和被测存储元件的多个锁存器之间进行接口，提供多路复用（MUX）级邻近每个锁存器的扫描输入端口，向锁存器的数据输入端口提供功能信号输入，通过激活ABIST使能信号并将ABIST使能信号传送到每个锁存器，将锁存器设置为ABIST模式，产生多个的ABIST测试信号与ABIST引擎并行地应用ABIST测试信号并且与锁存器的扫描输入端口并行，确定是否执行了一个或多个测试模式，并通过停用ABIST使能来将锁存器设置为正常运行模式信号。

8. 发明申请

US20070189061A1 Asymmetrical Random Access Memory Cell, Memory Comprising Asymmetrical Memory Cells And Method To Operate Such A Memory 失效
标题翻译：非对称随机存取存储器单元，包含非对称存储单元的存储器和操作这样的存储器的方法
公开(公告)号：US20070189061A1
公开(公告)日：2007-08-16
申请号：US11669369
申请日：2007-01-31
申请人： Stefan Buettner , Torsten Mahnke , Wolfgang Penth , Otto Wagner
发明人： Stefan Buettner , Torsten Mahnke , Wolfgang Penth , Otto Wagner
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： Asymmetrical random access memory cell, memory comprising asymmetrical memory cells and method to operate such a memory The invention relates to an asymmetrical random access memory cell (1) comprising cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (b1t, b1c) of a pair of complementary bit-lines, which are connected via a pass-transistors (21, 31), wherein said cross coupled inverters (2, 3) have different switching thresholds and exhibit asymmetrical physical behaviours, wherein an additional pass-transistor (4) is provided in series to one of the pass-transistors (21) between one of the nodes (22) and its dedicated bit-line (blc). Further the invention relates to a random access memory comprising such memory cells and to a method of operating such a memory.
摘要翻译：不对称随机存取存储器单元，包括不对称存储器单元的存储器和用于操作这种存储器的方法本发明涉及一种非对称随机存取存储单元（1），包括交叉耦合的反相器（2,3），它们在其节点（22,32））通过一对互补位线的分开的位线（b 1 t，b 1 c），其经由传输晶体管（21,31）连接，其中所述交叉耦合的反相器（2,3）具有不同的切换阈值并表现出不对称的物理行为，其中附加的传输晶体管（4）与节点（22）中的一个与其专用位线（blc）之间的一个传输晶体管（21）串联提供。此外，本发明涉及包括这种存储器单元的随机存取存储器以及操作这种存储器的方法。

9. 发明授权

US5764587A Static wordline redundancy memory device 失效
标题翻译：静态字线冗余存储设备
公开(公告)号：US5764587A
公开(公告)日：1998-06-09
申请号：US765987
申请日：1997-01-10
申请人： Stefan Buettner , Jurgen Pille , Dieter Wendel , Friedrich Christian Wernicke
发明人： Stefan Buettner , Jurgen Pille , Dieter Wendel , Friedrich Christian Wernicke
IPC分类号： G11C11/413 , G06F11/20 , G06F12/16 , G11C8/00 , G11C29/00 , G11C29/04
CPC分类号： G11C29/78 , G11C29/848
摘要： The invention relates to a memory device comprising a set of word decoders W, a set of wordline drivers WL, a plurality of switches S to connect a subset of the wordline drivers to the set of word decoders and storage means 5 for the storage of information indicative of a defective wordline. The wordline drivers include a predefined subset of wordline drivers which are to be used when none of the wordlines are defective and a plurality of second subsets of wordline drivers which are to be used when one of the wordlines is defective. The memory device further includes logic means 4 for logically and permanently assigning one of the subsets to the set of word decoders in response to the information stored in the storage means, by controlling the switches S to connect one of the second subsets of wordline drivers to the set of word decoders.
摘要翻译： PCT No.PCT / EP95 / 02183 Sec。 371日期1997年1月10日 102（e）日期1997年1月10日PCT归档1995年6月7日PCT公布。公开号WO96 / 41264 日期：1996年12月19日本发明涉及包括一组字解码器W，一组字线驱动器WL，多个开关S以将字线驱动器的子集连接到一组字解码器和存储装置5的存储器件用于存储指示有缺陷的字线的信息。字线驱动器包括字线驱动器的预定义子集，当字线不是有缺陷时要使用的字线驱动器的子集，以及当字线之一有缺陷时要使用的多个字线驱动器的第二子集。存储装置还包括逻辑装置4，用于通过控制开关S将字线驱动器的第二子集中的一个连接到字线驱动器的一个，将逻辑上和永久地将一个子集合分配给字解码器集合，以响应存储在存储装置中的信息一组字解码器。

10. 发明授权

US10046375B2 Tool components and related machines and methods 有权
公开(公告)号：US10046375B2
公开(公告)日：2018-08-14
申请号：US13240367
申请日：2011-09-22
申请人： Stefan Buettner , Wolfgang Laib , Arnim Bruechle , Markus Hees , Yakup Coskun
发明人： Stefan Buettner , Wolfgang Laib , Arnim Bruechle , Markus Hees , Yakup Coskun
IPC分类号： B26F1/14 , B21D28/14 , B21D28/26 , B21D28/34 , B23Q17/00
摘要： In some aspects of the invention, tool components for processing of plate-like workpieces, the tool component include an end face adjoined by a tool region provided for regrinding, the tool region being configured to undergo regrinding as a result of wear; and at least one identification mark located on the tool component to indicate the amount of shortening of the tool region as a result of regrinding.

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