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1. 发明申请

US20020050407A1 Ground via structures in semiconductor packages 审中-公开
标题翻译：通过半导体封装中的结构接地
公开(公告)号：US20020050407A1
公开(公告)日：2002-05-02
申请号：US10013177
申请日：2001-12-07
申请人： SIGNETICS KP CO., LTD.
发明人： Ju Yung Sohn , Seung Ryul Ryu
IPC分类号： H01L023/52 , H05K001/11 , H01R012/04
CPC分类号： H01L24/49 , H01L23/3128 , H01L23/36 , H01L23/544 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2223/54473 , H01L2223/54486 , H01L2224/16225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48247 , H01L2224/48465 , H01L2224/49109 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/15157 , H01L2924/15162 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/15321 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H05K1/0219 , H05K3/3436 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/45099 , H01L2224/0401
摘要： A package for a semiconductor chip is provided. The package includes a ground conducting layer. A one metal layer interconnect substrate is attached to the ground conducting layer. The one metal layer interconnect substrate includes a via hole defining a path to the ground conducting layer. A conductive material substantially filling the path defined by the via hole is provided. The conductive material is in contact with the ground conducting layer.
摘要翻译：提供了一种用于半导体芯片的封装。该封装包括一个接地导电层。一个金属层互连衬底附接到接地导电层。一个金属层互连衬底包括限定到接地导电层的路径的通孔。提供了基本上填充由通孔限定的路径的导电材料。导电材料与接地导电层接触。

2. 发明公开

EP1019960A4 BALL GRID ARRAY SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME 失效
标题翻译： HERBLEITER-KUGELMATRIXPACKUNG UND HERSTELLUNGSVERFAHRENDAFÜR
公开(公告)号：EP1019960A4
公开(公告)日：2002-03-20
申请号：EP98920999
申请日：1998-05-05
申请人： SIGNETICS KP CO LTD
发明人： KARNEZOS MARCOS
IPC分类号： H01L23/12 , H01L23/31 , H01L23/36 , H01L23/48 , H01L23/544 , H05K1/02 , H05K3/34 , H01L23/498 , H01L23/52 , H01L29/40
CPC分类号： H01L24/49 , H01L23/3128 , H01L23/36 , H01L23/544 , H01L24/48 , H01L24/73 , H01L2223/54473 , H01L2223/54486 , H01L2224/16 , H01L2224/16225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48465 , H01L2224/49109 , H01L2224/73253 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01021 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/15153 , H01L2924/15157 , H01L2924/15162 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H05K1/0219 , H05K3/3436 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： Disclosed is a semiconductor package that includes a heat spreader (110). The package further includes a ground plane (160) having a first side that is attached to the heat spreader with an elctrically insulating adhesive (127). The ground plane has a first aperture (166a) defining a path to a surface of the heat spreader tthat is configured to receive a semiconductor die. An interconnect substrate (125) is adhesively attached to the ground plane, and the interconnect substrate has a second apperture (154) over the first aperture of the ground plane. Preferably, the interconnect substrate has a plurality of metal patterns (118) for electrically interconnecting the semiconductor die to electrical connections that are external to the package. The package further includes at least one conductively filled via (119) that is defined through the interconnect substrate and is in electrical contact with the ground plane. A second side of the ground plane includes patterned wettable pads over selected regions that are in electrical contact with at least one via.
摘要翻译：公开了一种半导体封装结构。封装结构包括散热器，用于散发在半导体封装结构内产生的热量。该封装还包括接地平面，该接地平面具有用电绝缘粘合剂附接到散热器的第一侧。接地平面具有限定到散热器的表面的路径的第一孔，其构造成接收半导体管芯。互连基板粘合地附接到接地平面，并且互连基板在接地平面的第一孔上方具有互补的第二孔。优选地，互连衬底具有用于将半导体管芯电连接到半导体封装结构外部的电连接的多个金属图案。封装结构还包括至少一个通过互连衬底限定的导电填充通孔，并且与接地平面电接触以建立与互连衬底的多个金属图案中的选定的金属图案的直接接地连接。优选地，接地平面的第二侧包括在与通过互连衬底限定的至少一个导电填充的通孔电接触的选定区域上的图案化的可润湿压板。

3. 发明公开

EP1019960A1 BALL GRID ARRAY SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME 失效
标题翻译：半导体封装与球矩阵处理用于生产
公开(公告)号：EP1019960A1
公开(公告)日：2000-07-19
申请号：EP98920999.4
申请日：1998-05-05
申请人： Signetics KP Co., Ltd.
发明人： KARNEZOS, Marcos
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/49 , H01L23/3128 , H01L23/36 , H01L23/544 , H01L24/48 , H01L24/73 , H01L2223/54473 , H01L2223/54486 , H01L2224/16 , H01L2224/16225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48465 , H01L2224/49109 , H01L2224/73253 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01021 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/15153 , H01L2924/15157 , H01L2924/15162 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H05K1/0219 , H05K3/3436 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： Disclosed is a semiconductor package that includes a heat spreader (110). The package further includes a ground plane (160) having a first side that is attached to the heat spreader with an elctrically insulating adhesive (127). The ground plane has a first aperture (166a) defining a path to a surface of the heat spreader tthat is configured to receive a semiconductor die. An interconnect substrate (125) is adhesively attached to the ground plane, and the interconnect substrate has a second apperture (154) over the first aperture of the ground plane. Preferably, the interconnect substrate has a plurality of metal patterns (118) for electrically interconnecting the semiconductor die to electrical connections that are external to the package. The package further includes at least one conductively filled via (119) that is defined through the interconnect substrate and is in electrical contact with the ground plane. A second side of the ground plane includes patterned wettable pads over selected regions that are in electrical contact with at least one via.

4. 发明专利

AU7370398A Ball grid array semiconductor package and method for making the same 未知
公开(公告)号：AU7370398A
公开(公告)日：1998-11-27
申请号：AU7370398
申请日：1998-05-05
申请人： SIGNETICS KP CO LTD
发明人： KARNEZOS MARCOS
IPC分类号： H01L23/12 , H01L23/31 , H01L23/36 , H01L23/48 , H01L23/544 , H05K1/02 , H05K3/34 , H01L23/52 , H01L29/40
摘要： Disclosed is a semiconductor package arrangement. The package arrangement includes a heat spreader for dissipating heat generated within the semiconductor package arrangement. The package further includes a ground plane having a first side that is attached to the heat spreader with an electrically insulating adhesive. The ground plane has a first aperture defining a path to a surface of the heat spreader that is configured to receive a semiconductor die. An interconnect substrate is adhesively attached to the ground plane, and the interconnect substrate has a complementary second aperture over the first aperture of the ground plane. Preferably, the interconnect substrate has a plurality of metal patterns for electrically interconnecting the semiconductor die to electrical connections that are external to the semiconductor package arrangement. The package arrangement further includes at least one conductively filled via that is defined through the interconnect substrate and is in electrical contact with the ground plane to establish a direct ground connection from selected ones of the plurality of metal patterns of the interconnect substrate. Preferably, a second side of the ground plane includes patterned wetable platting pads over selected regions that are in electrical contact with the at least one conductively filled via that is defined through the interconnect substrate.

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