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1. 发明授权

US08035112B1 SIC power DMOSFET with self-aligned source contact 有权
标题翻译：具有自对准源极接触的SIC功率DMOSFET
公开(公告)号：US08035112B1
公开(公告)日：2011-10-11
申请号：US12429176
申请日：2009-04-23
申请人： James A. Cooper , Asmita Saha
发明人： James A. Cooper , Asmita Saha
IPC分类号： H01L21/0312
CPC分类号： H01L29/7802 , H01L23/544 , H01L29/0878 , H01L29/41741 , H01L29/4238 , H01L29/45 , H01L29/66068 , H01L2223/54426 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： An intermediate product in the fabrication of a MOSFET, including a silicon carbide wafer having a substrate and a drift layer on said substrate, said drift layer having a plurality of source regions formed adjacent an upper surface thereof; a first oxide layer on said upper surface of said drift layer; a plurality of polysilicon gates above said first oxide layer, said plurality of polysilicon gates including a first gate adjacent a first of said source regions; an oxide layer over said first source region of greater thickness than said first oxide layer; and, an oxide layer over said first gate of substantially greater thickness than said oxide layer over said first source region.
摘要翻译：一种制造MOSFET的中间产品，包括在所述衬底上具有衬底和漂移层的碳化硅晶片，所述漂移层具有邻近其上表面形成的多个源极区; 在所述漂移层的所述上表面上的第一氧化物层; 在所述第一氧化物层之上的多个多晶硅栅极，所述多个多晶硅栅极包括与所述源极区域中的第一个相邻的第一栅极; 所述第一源区上的氧化物层的厚度大于所述第一氧化物层的厚度; 以及在所述第一栅极上方的氧化层，其厚度大于所述第一源极区上的所述氧化物层的厚度。

2. 发明授权

US07498633B2 High-voltage power semiconductor device 有权
标题翻译：高压功率半导体器件
公开(公告)号：US07498633B2
公开(公告)日：2009-03-03
申请号：US11338007
申请日：2006-01-23
申请人： James A. Cooper , Asmita Saha
发明人： James A. Cooper , Asmita Saha
IPC分类号： H01L29/94
CPC分类号： H01L29/7802 , H01L29/0696 , H01L29/0878 , H01L29/1608
摘要： A semiconductor device, such as a metal-oxide semiconductor field-effect transistor, includes a semiconductor substrate, a drift layer formed on the substrate, a first and a second source region, and a JFET region defined between the first and the second source regions. The JFET region may have a short width and/or a higher concentration of impurities than the drift layer. The semiconductor device may also include a current spreading layer formed on the drift layer. The current spreading layer may also have a higher concentration of impurities than the drift layer.
摘要翻译：诸如金属氧化物半导体场效应晶体管的半导体器件包括半导体衬底，形成在衬底上的漂移层，第一和第二源极区以及限定在第一和第二源极区之间的JFET区。 JFET区可能具有比漂移层短的宽度和/或更高的杂质浓度。半导体器件还可以包括形成在漂移层上的电流扩散层。电流扩散层也可以具有比漂移层更高的杂质浓度。

3. 发明授权

US4715422A Reinforcement of articles of cast metal or metal alloy 失效
标题翻译：铸造金属或金属合金制品的加固
公开(公告)号：US4715422A
公开(公告)日：1987-12-29
申请号：US852099
申请日：1986-04-14
申请人： Norman Tommis , James A. Cooper
发明人： Norman Tommis , James A. Cooper
IPC分类号： B22D19/14 , C04B26/00 , C04B38/06 , C22C47/00 , C22C47/02 , C22C47/06 , C22C47/08 , C22C47/12
CPC分类号： C22C47/025 , B22D19/14 , C04B26/00 , C04B38/0645 , C22C47/06 , C22C47/08 , B22F2998/00 , C04B2111/00931 , Y10T29/49259
摘要： Milled silica or alumina fibres or whiskers are formed into a reinforcement for a squeeze cast article such as a piston for an internal combustion engine. The problem of handling the milled fibres or whiskers while they are formed into the reinforcement is mitigated or overcome by the use of coagulated latex to bind the milled fibres or whiskers in a colloidal silica solution until they are fired to form the reinforcement. In addition, a starch is used to prevent the milled fibres or whiskers settling when in the colloidal silica solution.
摘要翻译：将磨碎的二氧化硅或氧化铝纤维或晶须形成为挤压铸造制品例如用于内燃机的活塞的增强件。研磨的纤维或晶须在形成加强件时的处理问题通过使用凝结的胶乳将胶合二氧化硅溶液中的研磨的纤维或晶须结合到它们被烧制以形成增强物来缓解或克服。此外，当在胶体二氧化硅溶液中时，使用淀粉来防止研磨的纤维或晶须沉降。

4. 发明授权

US4139907A Integrated read only memory 失效
标题翻译：集成只读存储器
公开(公告)号：US4139907A
公开(公告)日：1979-02-13
申请号：US829570
申请日：1977-08-31
申请人： Donald E. Blahut , James A. Cooper, Jr.
发明人： Donald E. Blahut , James A. Cooper, Jr.
IPC分类号： G11C17/00 , G11C17/12 , H01L21/8246 , H01L27/112 , G11C11/40
CPC分类号： G11C17/12 , H01L27/112
摘要： The word conductors of a semiconductor integrated ROM are foreshortened where permitted by the organization of data in the memory. The space made available by the eliminated portions of the word conductors is used for electrical connection to the bit conductors from the sides of the array rather than at the ends. A space reduction of about thirty percent is achieved.
摘要翻译： {PG，1半导体集成ROM的字导体在存储器中的数据组织允许的情况下被缩短。由字导体的消除部分提供的空间用于从阵列的侧面而不是端部与位导体电连接。实现了大约30％的空间减少。

5. 发明申请

US20130292149A1 SYSTEM FOR MOUNTING AN ELECTRICAL FIXTURE TO AN ELECTRICAL JUNCTION BOX 有权
标题翻译：将电气装置安装到电气接线盒的系统
公开(公告)号：US20130292149A1
公开(公告)日：2013-11-07
申请号：US13980011
申请日：2012-01-17
申请人： James A. Cooper , Hon Man Kuan
发明人： James A. Cooper , Hon Man Kuan
IPC分类号： H02G3/16 , H02G1/00
CPC分类号： H02G3/16 , F21V21/03 , H02G1/00 , H02G3/14 , H02G3/18 , H02G3/20 , Y10T29/49208
摘要： The invention provides a mount for installing an electrical fixture to an electrical junction box. The mount includes a support configured for independent attachment to said junction box and said electrical fixture respectively for mounting said fixture to said junction box. The mount further includes at least one electrical quick connect member engaged to said support comprising a first connection element for forming an electrical connection with a electrical wire and a second connection element for forming an electrical connection a fixture electrical wires. The first and second connection elements are electrically connected or connectible together to form an electrical connection between the source wires and the fixture wires.
摘要翻译：本发明提供了一种用于将电气安装件安装到电接线盒的安装座。安装座包括支撑件，其构造成用于独立地附接到所述接线盒和所述电气固定件，用于将所述固定件安装到所述接线盒。该安装件还包括与所述支撑件接合的至少一个电快速连接构件，其包括用于与电线形成电连接的第一连接元件和用于形成固定电线的电连接的第二连接元件。第一和第二连接元件电连接或连接在一起以在源极线和夹具线之间形成电连接。

6. 发明授权

US06902947B2 Integrated method for release and passivation of MEMS structures 失效
标题翻译： MEMS结构的释放和钝化的集成方法
公开(公告)号：US06902947B2
公开(公告)日：2005-06-07
申请号：US10435757
申请日：2003-05-09
申请人： Jeffrey D. Chinn , Rolf A. Guenther , Michael B. Rattner , James A. Cooper , Toi Yue Becky Leung , Claes H. Bjorkman
发明人： Jeffrey D. Chinn , Rolf A. Guenther , Michael B. Rattner , James A. Cooper , Toi Yue Becky Leung , Claes H. Bjorkman
IPC分类号： B81B3/00 , B81C1/00 , H01L21/00
CPC分类号： B81C1/0096 , B81B3/0005 , B81C2201/0176 , B81C2201/112 , B82Y30/00
摘要： Disclosed herein is a method of improving the adhesion of a hydrophobic self-assembled monolayer (SAM) coating to a surface of a MEMS structure, for the purpose of preventing stiction. The method comprises treating surfaces of the MEMS structure with a plasma generated from a source gas comprising oxygen and, optionally, hydrogen. The treatment oxidizes the surfaces, which are then reacted with hydrogen to form bonded OH groups on the surfaces. The hydrogen source may be present as part of the plasma source gas, so that the bonded OH groups are created during treatment of the surfaces with the plasma. Also disclosed herein is an integrated method for release and passivation of MEMS structures which may be adjusted to be carried out in a either a single chamber processing system or a multi-chamber processing system.
摘要翻译：本文公开了一种改进疏水性自组装单层（SAM）涂层到MEMS结构表面的粘附性的方法，以防止粘结。该方法包括用包含氧气和任选的氢气的源气体产生的等离子体处理MEMS结构的表面。处理氧化表面，然后与氢气反应以在表面上形成键合的OH基团。氢源可以作为等离子体源气体的一部分存在，使得在用等离子体处理表面期间产生结合的OH基团。本文还公开了一种用于MEMS结构的释放和钝化的集成方法，其可以被调整为在单室处理系统或多室处理系统中进行。

7. 发明授权

US4626708A Electronic logic to enhance switch reliability in detecting openings and closures of redundant switches 失效
标题翻译：用于提高开关可靠性的电子逻辑，用于检测冗余开关的开关和闭合
公开(公告)号：US4626708A
公开(公告)日：1986-12-02
申请号：US572338
申请日：1984-01-20
申请人： James A. Cooper
发明人： James A. Cooper
IPC分类号： G06F11/00 , G06F11/16 , H03K19/20 , H03K19/003 , G06F7/02 , H04L1/00
CPC分类号： G06F11/0796 , G06F11/0751 , G06F11/16 , H03K19/20
摘要： A logic circuit is used to enhance redundant switch reliability. Two or more switches are monitored for logical high or low output. The output for the logic circuit produces a redundant and failsafe representation of the switch outputs. When both switch outputs are high, the output is high. Similarly, when both switch outputs are low, the logic circuit's output is low. When the output states of the two switches do not agree, the circuit resolves the conflict by memorizing the last output state which both switches were simultaneously in and produces the logical complement of this output state. Thus, the logic circuit of the present invention allows the redundant switches to be treated as if they were in parallel when the switches are open and as if they were in series when the switches are closed. A failsafe system having maximum reliability is thereby produced.
摘要翻译：逻辑电路用于增强冗余开关的可靠性。监视两个或多个开关以进行逻辑高或低输出。逻辑电路的输出产生交换机输出的冗余和故障保护表示。当两个开关输出为高电平时，输出为高电平。类似地，当两个开关输出都为低电平时，逻辑电路的输出为低电平。当两个开关的输出状态不一致时，电路通过记忆两个开关同时处于最后的输出状态来解决冲突，并产生该输出状态的逻辑补码。因此，本发明的逻辑电路允许冗余开关被当作开关处于并联状态，并且当开关闭合时它们是串联的。由此产生具有最高可靠性的故障安全系统。

8. 发明授权

US4324038A Method of fabricating MOS field effect transistors 失效
标题翻译：制造MOS场效应晶体管的方法
公开(公告)号：US4324038A
公开(公告)日：1982-04-13
申请号：US209755
申请日：1980-11-24
申请人： Chuan C. Chang , James A. Cooper, Jr. , Dawon Kahng , Shyam P. Murarka
发明人： Chuan C. Chang , James A. Cooper, Jr. , Dawon Kahng , Shyam P. Murarka
IPC分类号： H01L21/285 , H01L21/336 , H01L29/423 , H01L29/78 , H01L21/28
CPC分类号： H01L29/66621 , H01L21/28537 , H01L29/66643 , H01L29/7839
摘要： A method for making a MOSFET device (20) in a semiconductor body (10) includes the step of forming source and drain contact electrodes (12.1, 12.2) prior to growth of the gate oxide (10.3) and after formation of a high conductivity surface region (10.5). The exposed mutually opposing sidewall edges of each of the contact electrodes (12.1, 12.2) are coated with a sidewall silicon dioxide layer (15.1, 15.2), and the then exposed surface of the semiconductor body (10) between these sidewalls is etched to depth beneath the high conductivity surface region (10.5) in order to separate it into the source and drain regions (10.1, 10.2).Formation of the high conductivity region may be omitted by using Schottky barrier or impurity doped material for the contact electrodes (12.1, 12.2).
摘要翻译：在半导体本体（10）中制造MOSFET器件（20）的方法包括在栅极氧化物（10.3）生长之前和形成高电导率表面之后形成源极和漏极接触电极（12.1,12.2）的步骤地区（10.5）。每个接触电极（12.1,12.2）的暴露的相互相对的侧壁边缘被涂覆有侧壁二氧化硅层（15.1,15.2），并且将这些侧壁之间的半导体本体（10）的暴露的表面蚀刻到深度在高导电性表面区域（10.5）之下，以将其分离成源极和漏极区域（10.1,10.2）。通过使用用于接触电极（12.1,12.2）的肖特基势垒或杂质掺杂材料，可以省略高导电性区域的形成。

9. 发明申请

US20110151649A1 METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20110151649A1
公开(公告)日：2011-06-23
申请号：US12961410
申请日：2010-12-06
申请人： James A. Cooper , Xiaokun Wang
发明人： James A. Cooper , Xiaokun Wang
IPC分类号： H01L21/20
CPC分类号： H01L29/7395
摘要： A method for fabricating a semiconductor device includes forming a first semiconductor layer on a front side of the semiconductor substrate. Additional semiconductor layers may be formed on a font side of the first semiconductor layer. The substrate is subsequently removed. In some embodiments, one or more additional semiconductor layers may be formed on the back side of the first semiconductor layer after the semiconductor substrate has been removed. Additionally, in some embodiments, a portion of the first semiconductor layer is removed along with the semiconductor substrate. In such embodiments, the first semiconductor layer is subsequently etched to a known thickness. Source regions and device electrodes may be then be formed.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底的前侧形成第一半导体层。另外的半导体层可以形成在第一半导体层的字体侧上。随后除去衬底。在一些实施例中，在去除半导体衬底之后，可以在第一半导体层的背面上形成一个或多个附加的半导体层。另外，在一些实施例中，第一半导体层的一部分与半导体衬底一起被去除。在这样的实施例中，第一半导体层随后被蚀刻到已知的厚度。然后可以形成源区和器件电极。

10. 发明授权

US06579552B1 Compressed bale method 失效
标题翻译：压缩捆包法
公开(公告)号：US06579552B1
公开(公告)日：2003-06-17
申请号：US09661102
申请日：2000-09-13
申请人： Roger R. Myhre , Lawrence K. Cooper , Jeffrey K. Cooper , Daniel L. Peterson , James A. Cooper
发明人： Roger R. Myhre , Lawrence K. Cooper , Jeffrey K. Cooper , Daniel L. Peterson , James A. Cooper
IPC分类号： A01F1500
CPC分类号： A01F15/00 , A01F15/005 , Y10T83/0505
摘要： The present invention relates to a method for forming a compressed and cut bale of fibrous material, whereby the bale of fibrous material has at least one cut that allows the material to be separated into two distinct and separate layers. The present invention also relates to the compressed and cut fibrous material.
摘要翻译：本发明涉及一种用于形成压缩和切割的纤维材料包的方法，由此纤维材料束具有至少一个允许将材料分离成两个不同且分离的层的切口。本发明还涉及压缩和切割的纤维材料。

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