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1. 发明申请

WO2007078923A2 CRYPTOGRAPHY PROCESSING UNITS AND MULTIPLIER 审中-公开
标题翻译：图像处理单元和多路复用器
公开(公告)号：WO2007078923A2
公开(公告)日：2007-07-12
申请号：PCT/US2006/048293
申请日：2006-12-18
申请人： INTEL CORPORATION , HASENPLAUGH, William, C. , CUTTER, Daniel, F. , FEGHALI, Wajdi, K. , WOLRICH, Gilbert, M. , GAUBATZ, Gunnar , GOPAL, Vinodh
发明人： HASENPLAUGH, William, C. , CUTTER, Daniel, F. , FEGHALI, Wajdi, K. , WOLRICH, Gilbert, M. , GAUBATZ, Gunnar , GOPAL, Vinodh
IPC分类号： G06F9/38
CPC分类号： G06F7/52 , G06F9/3001 , G06F9/3881 , G06F9/3885 , G06F21/72
摘要： In general, in one aspect, the disclosure describes a system including multiple programmable processing units, a dedicated hardware multiplier, and at least one bus connecting the multiple processing units and multiplier.
摘要翻译：通常，在一个方面，本公开描述了包括多个可编程处理单元，专用硬件乘法器和连接多个处理单元和乘法器的至少一个总线的系统。

2. 发明申请

WO2007078923A3 CRYPTOGRAPHY PROCESSING UNITS AND MULTIPLIER 审中-公开
标题翻译：图像处理单元和多路复用器
公开(公告)号：WO2007078923A3
公开(公告)日：2007-10-18
申请号：PCT/US2006048293
申请日：2006-12-18
申请人： INTEL CORP , HASENPLAUGH WILLIAM C , CUTTER DANIEL F , FEGHALI WAJDI K , WOLRICH GILBERT M , GAUBATZ GUNNAR , GOPAL VINODH
发明人： HASENPLAUGH WILLIAM C , CUTTER DANIEL F , FEGHALI WAJDI K , WOLRICH GILBERT M , GAUBATZ GUNNAR , GOPAL VINODH
IPC分类号： G06F9/30 , G06F7/52
CPC分类号： G06F7/52 , G06F9/3001 , G06F9/3881 , G06F9/3885 , G06F21/72
摘要： In general, in one aspect, the disclosure describes a cryptographic system including multiple programmable processing units, a dedicated hardware multiplier, and at least one bus connecting the multiple processing units and multiplier.
摘要翻译：通常，一方面，本公开描述了一种包括多个可编程处理单元，专用硬件乘法器和连接多个处理单元和乘法器的至少一个总线的密码系统。

3. 发明申请

WO2007078939A2 MULTIPLIER 审中-公开
标题翻译：乘数
公开(公告)号：WO2007078939A2
公开(公告)日：2007-07-12
申请号：PCT/US2006/048417
申请日：2006-12-18
申请人： INTEL CORPORATION , FEGHALI, Wajdi, K. , HASENPLAUGH, William, C. , WOLRICH, Gilbert, M. , CUTTER, Daniel, F. , GOPAL, Vinodh , GAUBATZ, Gunnar
发明人： FEGHALI, Wajdi, K. , HASENPLAUGH, William, C. , WOLRICH, Gilbert, M. , CUTTER, Daniel, F. , GOPAL, Vinodh , GAUBATZ, Gunnar
IPC分类号： G06F7/525
CPC分类号： G06F7/5275
摘要： In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.
摘要翻译：一般来说，在一个方面，本发明描述了一种乘法器，其包括并行配置的一组多个乘法器，其中多个乘法器的集合具有对第一操作数的访问和第二操作数的乘法，第一操作数具有多个段，第二操作数具有多个段具有多个段的操作数。所述乘法器还包括逻辑以将所述第二操作数的单个段重复地提供给所述多个乘法器集合的每个乘法器，并且将所述第一操作数的多个相应段提供给所述多个乘法器组中的各个乘法器，直到所述第二操作数已被提供给第一个操作数的每个段。该逻辑至少部分地基于第一操作数内的相应段的位置来移动多个乘法器组中不同的乘法器的输出。乘法器还包括耦合到逻辑的累加器。

4. 发明申请

WO2007078939A3 MULTIPLIER 审中-公开
标题翻译：乘数
公开(公告)号：WO2007078939A3
公开(公告)日：2007-11-15
申请号：PCT/US2006048417
申请日：2006-12-18
申请人： INTEL CORP , FEGHALI WAJDI K , HASENPLAUGH WILLIAM C , WOLRICH GILBERT M , CUTTER DANIEL F , GOPAL VINODH , GAUBATZ GUNNAR
发明人： FEGHALI WAJDI K , HASENPLAUGH WILLIAM C , WOLRICH GILBERT M , CUTTER DANIEL F , GOPAL VINODH , GAUBATZ GUNNAR
IPC分类号： G06F7/525
CPC分类号： G06F7/5275
摘要： In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.
摘要翻译：通常，在一个方面，本公开描述了一种乘法器，该乘法器包括并行配置的一组多个乘法器，其中多个乘法器的集合可以访问第一操作数和第二操作数以便相乘，第一操作数具有多个段并且第二操作数操作数有多个段。乘法器还包括逻辑，用于重复提供第二操作数的单个段到该组多个乘法器中的每个乘法器，并且将第一操作数的多个相应段提供给该多个乘法器集中的相应乘法直到第二个操作数已经与第一个操作数的每个段一起提供。该逻辑至少部分地基于第一操作数内的各个段的位置来移位该多个乘法器组中的不同者的输出。乘法器还包括一个连接到逻辑的累加器。

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