基本信息:
- 专利标题： STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH PARALLEL WINDOWS
- 专利标题（中）：具有平行窗口的多芯线绕组组合的最小化
- 申请号：PCT/US2012/057905 申请日：2012-09-28
- 公开(公告)号：WO2013052372A2 公开(公告)日：2013-04-11
- 发明人： CRISP, Richard, Dewitt , ZOHNI, Wael , HABA, Belgacem , LAMBRECHT, Frank
- 申请人： INVENSAS CORPORATION
- 申请人地址： 2702 Orchard Parkway San Jose, CA 95134 US
- 专利权人： INVENSAS CORPORATION
- 当前专利权人： INVENSAS CORPORATION
- 当前专利权人地址： 2702 Orchard Parkway San Jose, CA 95134 US
- 代理机构： KARLIN, Joseph H. et al.
- 优先权： US13/440,515 20120405; US61/542,553 20111003; US13/337,565 20111227; US137337,575 20111227
摘要：
A microelectronic package 10 can include a substrate 20 having first and second surfaces 21, 22 and first and second apertures 26a, 26b extending therebetween, first and second microelectronic elements 30a, 30b each having a surface 31 facing the first surface, terminals 25a exposed at the second surface in a central region 23 thereof, and leads 40 electrically connected between contacts 35 exposed at the surface of each microelectronic element and the terminals. The apertures 26a, 26b can have first and second parallel axes 29a, 29b extending in directions of the lengths of the respective apertures. The central region 23 of the second surface 22 can be disposed between the first and second axes 29a, 29b. The terminals 25a can be configured to carry address information usable by circuitry within the microelectronic package 10 to determine an addressable memory location from among all the available addressable memory locations of a memory storage array of at least one of the microelectronic elements 30a, 30b.
摘要（中）：
微电子封装10可以包括具有第一和第二表面21,22的衬底20和在其间延伸的第一和第二孔26a，26b，第一和第二微电子元件30a，30b，每个具有面向第一表面的表面31， 在其中央区域23中的第二表面和电连接在暴露在每个微电子元件的表面处的触点35和端子之间的引线40。 孔26a，26b可以具有在相应孔的长度方向上延伸的第一和第二平行轴线29a，29b。 第二表面22的中心区域23可以设置在第一和第二轴线29a，29b之间。 终端25a可以被配置为承载可由微电子封装10内的电路使用的地址信息，以从微电子元件30a，30b中的至少一个的存储器存储阵列的所有可寻址的存储器单元中确定可寻址的存储器位置。