发明申请
WO2010136995A1 METHOD AND APPARATUS FOR ALIGNING A SERIAL BIT STREAM WITH A PARALLEL OUTPUT
审中-公开
基本信息:
- 专利标题: METHOD AND APPARATUS FOR ALIGNING A SERIAL BIT STREAM WITH A PARALLEL OUTPUT
- 专利标题(中):用于对准具有并行输出的串行位流的方法和装置
- 申请号:PCT/IB2010/052376 申请日:2010-05-27
- 公开(公告)号:WO2010136995A1 公开(公告)日:2010-12-02
- 发明人: BRUNNER, Robert , GORDON, David , JULIEN, Martin , BELIVEAU, Ludovic
- 申请人: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL) , BRUNNER, Robert , GORDON, David , JULIEN, Martin , BELIVEAU, Ludovic
- 申请人地址: SE-164 83 Stockholm SE
- 专利权人: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL),BRUNNER, Robert,GORDON, David,JULIEN, Martin,BELIVEAU, Ludovic
- 当前专利权人: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL),BRUNNER, Robert,GORDON, David,JULIEN, Martin,BELIVEAU, Ludovic
- 当前专利权人地址: SE-164 83 Stockholm SE
- 代理机构: NICOLAESCU, Alex et al.
- 优先权: US12/475,250 20090529
- 主分类号: H04J3/06
- IPC分类号: H04J3/06 ; H03M9/00 ; H04L7/04
摘要:
The invention relates to a method and circuit for aligning a serial bit stream with a parallel output. The method comprises latching Q bits from the serial bit stream into a register, locating a position P of a first bit of a start of frame delimiter (SFD) in the register and discarding P-1 bits from the serial bit stream, before the position of the first bit of the SFD, thereby aligning the serial bit stream with the parallel output. The circuit comprises a latch, a fault tolerant analysis logic (FTAL) for locating a position P of a first bit of a start of frame delimiter (SFD) in the register and a shift register for discarding P-I bits from the serial bit stream, before the position of the first bit of the SFD, thereby aligning the serial bit stream with the parallel output.
摘要(中):
本发明涉及一种用于将串行比特流与并行输出对准的方法和电路。 该方法包括将Q位从串行比特流锁定到寄存器中,在位置之前定位寄存器中的起始帧定界符(SFD)的第一位的位置P,并从串行位流中丢弃P-1位 的SFD的第一位,从而使串行比特流与并行输出对齐。 该电路包括锁存器,用于定位寄存器中的起始帧定界符(SFD)的第一位的位置P的容错分析逻辑(FTAL)和用于从串行位流中丢弃PI位的移位寄存器 SFD的第一位的位置,从而使串行比特流与并行输出对齐。