发明申请
US20210035859A1 TRENCHES IN WAFER LEVEL PACKAGES FOR IMPROVEMENTS IN WARPAGE RELIABILITY AND THERMALS
有权
基本信息:
- 专利标题： TRENCHES IN WAFER LEVEL PACKAGES FOR IMPROVEMENTS IN WARPAGE RELIABILITY AND THERMALS
- 申请号：US16526012 申请日：2019-07-30
- 公开(公告)号：US20210035859A1 公开(公告)日：2021-02-04
- 发明人： Vipul MEHTA , Yiqun BAI , Ziyin LIN , John DECKER , Yan LI
- 申请人： Intel Corporation
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 主分类号： H01L21/768
- IPC分类号： H01L21/768 ; H01L21/56 ; H01L23/31 ; H01L23/367 ; H01L23/373
摘要：
Embodiments disclosed herein include composite dies and methods of forming such composite dies. In an embodiment, a composite die comprises a base substrate, a first die over the base substrate, and a second die over the base substrate and adjacent to the first die. In an embodiment an underfill layer is between the first die and the base substrate, between the second die and the base substrate, and between the first die and the second die. In an embodiment, a trench into the underfill layer is between the first die and the second die. In an embodiment the composite die further comprises, a mold layer over the first die and the second die, wherein the mold layer fills the trench.
公开/授权文献:
IPC结构图谱:
| H | 电学 |
| --H01 | 基本电气元件 |
| ----H01L | 半导体器件；其他类目未包含的电固体器件 |
| ------H01L21/00 | 专门适用于制造或处理半导体或固体器件或其部件的方法或设备 |
| --------H01L21/67 | .专门适用于在制造或处理过程中处理半导体或电固体器件的装置；专门适合于在半导体或电固体器件或部件的制造或处理过程中处理晶片的装置 |
| ----------H01L21/71 | ..限定在组H01L21/70中的器件的特殊部件的制造 |
| ------------H01L21/768 | ...利用互连在器件中的分离元件间传输电流 |