基本信息:
- 专利标题： CLOCK DELAY DETECTING CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME
- 申请号：US14040829 申请日：2013-09-30
- 公开(公告)号：US20150015310A1 公开(公告)日：2015-01-15
- 发明人： Young Suk SEO
- 申请人： SK HYNIX INC.
- 申请人地址： KR Icheon-si
- 专利权人： SK HYNIX INC.
- 当前专利权人： SK HYNIX INC.
- 当前专利权人地址： KR Icheon-si
- 优先权： KR10-2013-0081562 20130711
- 主分类号： H03K5/159
- IPC分类号： H03K5/159 ; H03L7/06
摘要：
Provided is a clock delay detecting circuit and semiconductor apparatus using the same that is capable of generating a period signal whose period is a delay time of a clock, dividing the period signal, and counting the divided period signal. The clock delay detection circuit comprises a period signal generating unit configured to generate a counting control signal, a period signal dividing unit configured to generate a counting enable signal by dividing the counting control signal, and a counting unit configured to generate a delay information signal by counting the counting enable signal with a clock, wherein the counting control signal has a period with a predetermined time.
IPC结构图谱:
| H | 电学 |
| --H03 | 基本电子电路 |
| ----H03K | 脉冲技术 |
| ------H03K5/00 | 本小类中一个其他大组不包含的脉冲处理 |
| --------H03K5/159 | .以上各小组不包含的延迟线的应用 |